Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2009-02-17
2010-10-12
Mai, Son L (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S189070
Reexamination Certificate
active
07813194
ABSTRACT:
An apparatus and method for repairing a semiconductor memory device includes a first memory cell array, a first redundant cell array and a repair circuit configured to nonvolatilely store a first address designating at least one defective memory cell in the first memory cell array. A first volatile cache stores a first cached address corresponding to the first address designating the at least one defective memory cell. The repair circuit distributes the first address designating the at least one defective memory cell of the first memory cell array to the first volatile cache. Match circuitry substitutes at least one redundant memory cell from the first redundant cell array for the at least one defective memory cell in the first memory cell array when a first memory access corresponds to the first cached address.
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International Search Report for International Application No. PCT/US2006/023219 dated Nov. 17, 2006 (4 pages).
Keeth Brent
Manning Troy A.
Martin Chris G.
Mai Son L
Micro)n Technology, Inc.
TraskBritt
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