Apparatus and method for renaming a data block within a cache

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

Reexamination Certificate

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C711S145000, C711S165000

Reexamination Certificate

active

07111125

ABSTRACT:
A microprocessor apparatus is provided that enables exclusive allocation and renaming of a block of cache lines. The apparatus includes translation logic and execution logic. The translation logic translates a block allocate and rename instruction into a micro instruction sequence that directs a microprocessor to allocate a first block of cache lines in an exclusive state and to copy the contents of a second block of cache lines into the first block of cache lines. The execution logic is coupled to the translation logic. The execution logic receives the micro instruction sequence, and issues transactions over a memory bus that requests the first block of cache lines in the exclusive state. Upon granting of exclusive rights, the execution logic copies the contents of the second block of cache lines into the first block of cache lines.

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