Static information storage and retrieval – Read/write circuit – Data refresh
Reexamination Certificate
2000-09-08
2002-02-05
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Data refresh
C365S120000, C711S106000
Reexamination Certificate
active
06345009
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to memory systems. More particularly, this invention relates to an improved technique for performing a refresh operation in a memory system.
2. Description of the Related Art
Dynamic RAM (DRAM) devices require periodic refresh operations to retain data in their storage cells. A refresh operation consists of a row sense operation and a row precharge operation. Each memory cell needs to be refreshed within a given time interval known as T
ref
, the refresh period. A typical T
ref
value is 64 ms.
As the number of banks in memory devices increases and as the number of devices in memory systems increases, the issue rate of refresh commands sent from a memory controller also increases. This increased traffic due to refresh operations can introduce an overhead that unacceptably impacts performance, as measured by effective data bandwidth and memory access latency. For a given memory system, the number of refresh operations that need to be performed within T
ref
equals
∑
i
=
0
N
-
1
B
i
R
i
,
(
Eq
1
)
where N=maximum number of devices in the system, B
i
=the number of banks in device i, and R
i
=the number of rows per bank in device i. A design goal is to maintain a constant frequency of refresh commands over many DRAM generations so that channel overhead does not grow and complexity in the controller is minimized.
One general approach to reduce controller refresh overhead is to perform refresh operations in multiple devices using a single issued command. The simplest way to do this is with a broadcast refresh command, which triggers refresh operations in all devices in the system. With a single refresh command, more than one device can be either simultaneously or sequentially refreshed. From a performance standpoint, it is more desirable to refresh banks in each device simultaneously, so that the time that bank resources are tied up is minimized.
Simultaneous multi-device refresh, however, has its challenges. One challenge is the problem of current spikes. Each refresh operation for each device requires a certain amount of supply current over time.
FIG. 1
shows a typically current profile over time for a row sense operation. Note that very near time
0
, there is an initial spike of current. This spike is large because the row sensing circuits have been designed to access cell data as quickly as possible in order to minimize the latency to the first allowable page access to bits stored in the sense amps. This spike, characterized by rate of change in current, dI/dt, can cause noise problems in a DRAM, since current spikes can reduce the internal supply voltage. In addition, the current spike can cause failure in circuits on the same die or on other devices that share the same supply voltage.
It is common for memory devices in a memory system to share the same supply voltage.
FIG. 2
illustrates a set of memory devices
20
A-
20
N that share a common supply voltage Vdd. Without a sufficient bypass capacitor network
22
in the system, current spikes from each device can cause the supply voltage to vary, and with a shared supply, current spike noise can couple between memory devices. With multiple devices simultaneously doing refresh operations, the current spike effect can be additive, thus causing greater probability of circuit failure. The more devices performing the operation simultaneously, the bigger the potential problem. The amount of noise that can be tolerated varies depending on the bypass network and circuit designs.
In view of the foregoing, it would be highly desirable to provide a mechanism for reducing current spikes and related problems associated with memory refresh operations.
SUMMARY OF THE INVENTION
A memory system includes a set of memory devices. An interconnect structure links the set of memory devices to one another. A memory controller is connected to the interconnect structure. The memory controller is configured to apply a control signal to the interconnect structure such that a specified subset of the set of memory devices performs a refresh operation.
The selective refresh operation may be implemented with a device mask, which includes a single bit for each device in the system to specify whether each device performs the operation. This embodiment requires N bits to control N devices in the system and allows any arbitrary pattern of device operation. A second implementation utilizes a partial decode technique, which selects a subgroup of devices using X bits, where X<Y, Y=log2 N, and N=(max. # of devices in the system). Combinations of these two implementations are also possible.
The selective refresh operation of the invention helps reduce supply noise problems otherwise induced when many devices perform operations simultaneously.
REFERENCES:
patent: 5251177 (1993-10-01), Akamatsu et al.
patent: 5535169 (1996-07-01), Endo et al.
patent: 5940851 (1999-08-01), Leung
patent: 5999471 (1999-12-01), Choi
patent: 6178130 (2001-01-01), Tsern et al.
Anderson Andrew V.
Barth Richard M.
Davis Paul G.
Hampel Craig E.
Holman Thomas J.
Elms Richard
Nguyen Van-Thu
Pennie & Edmonds LLP
Rambus Inc.
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