Apparatus and method for reduction of power consumption in...

Details Apparatus and method for reduction of power consumption in... Apparatus and method for reduction of power consumption in...

2005-07-26

2005-07-26

Ellis, Kevin L. (Department: 2188)

Electrical computers and digital processing systems: memory

Address formation

Address mapping

Reexamination Certificate

active

06922769

ABSTRACT:
A method and apparatus for an apparatus and method for reduction of power consumption in OS that use flat segmentation memory model are described. In one embodiment, the method includes monitoring a segment register to detect a segment register update operation. Once the segment register update operation is detected, a code/data segment contained within the segment register is identified as one of a segmented code/data segment and a flat code/data segment. Once detected, the segment register is updated according to whether the segment is flat or segmented. Accordingly, when a segment register read is performed, one or more updated bits within the segment register are used to identify the code/data read from the segment register as either flat or segmented.

REFERENCES:
patent: 5768610 (1998-06-01), Pflum
patent: 6189068 (2001-02-01), Witt et al.
patent: 6463517 (2002-10-01), McGrath
patent: 2001/0037421 (2001-11-01), Singh et al.

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