Static information storage and retrieval – Read/write circuit – Testing
Patent
1997-02-19
1998-05-05
Nelms, David C.
Static information storage and retrieval
Read/write circuit
Testing
365190, 365205, 36518909, 365222, 365228, 365203, G11C 2900
Patent
active
057485445
ABSTRACT:
In a dynamic random access memory device, the time required for implementation of memory cell data retention time testing procedures can be reduced by changing the voltage level(s) applied to the components of the storage cell when compared to the voltages applied during the typical memory cell operation. By changing the voltage(s) applied to the components, the difference in the bitlines detected by the sense amplifier will be reduced. Because to the reduced bitline voltage difference, the decay of the charge on the storage cell causes a reduction in the data retention time. The data retention time is reduced in manner related to the typical memory cell operation. The altered voltage(s) can be applied to the storage cell bitlines and/or to the storage cell dummy capacitances.
REFERENCES:
patent: 5339277 (1994-08-01), McClure
patent: 5341336 (1994-08-01), McClure
Brady III W. James
Donaldson Richard L.
Holloway William W.
Nelms David C.
Texas Instruments Incorporated
LandOfFree
Apparatus and method for reducing test time of the data retentio does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for reducing test time of the data retentio, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for reducing test time of the data retentio will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-62605