Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
1998-08-05
2001-03-20
Pan, Daniel H. (Department: 2171)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C710S260000, C711S118000, C712S213000, C713S500000
Reexamination Certificate
active
06205518
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to apparatus and methods for reducing power consumption in a processor, and more particularly to circuits for reducing power consumption while a processor is executing an application code.
2. Background Art
Power management for processors is a significant consideration, particularly for portable computers where a battery provides the power. Techniques for conserving battery charge by low power operation generally involves power minimizing AC power consumption and standby power consumption. The primary method of driving the AC power has been through the use of low power circuits and technology permitting lower values of VDD. U.S. Pat. No. 4,615,005 issued Sep. 30, 1986 to Maejima et al. entitled DATA PROCESSING APPARATUS WITH CLOCK SIGNAL CONTROL BY MICROINSTRUCTION FOR REDUCED POWER CONSUMPTION AND METHOD THEREFOR discloses a method of controlling the supply of a clock signal to a logic circuit composed of CMOS gates for further reducing the power consumption by using a clock signal supply inhibit instruction.
U.S. Pat. No. 5,220,672 issued Jun. 15, 1993 to Nakao et al. entitled LOW POWER CONSUMING DIGITAL CIRCUIT DEVICE discloses a method for decreasing the power consumption of a digital circuit by interrupting the switching created by clock pulses and maintaining the system in a quiescent state.
U.S. Pat. No. 5,428,790 issued Jun. 27, 1995 to Harper et al. entitled COMPUTER POWER MANAGEMENT SYSTEM discloses a system for low power management for a portable computer that powers down various sections of the computer when they are not used.
U.S. Pat. No. 5,557,557 issued Sep. 17, 1996 to Frantz et al. entitled PROCESSOR POWER PROFILER discloses a method for determining the energy consumption of a processor when executing a program.
U.S. Pat. No. 5,560,024 issued Sep. 24, 1996 to Harper et al. entitled COMPUTER POWER MANAGEMENT SYSTEM discloses a system for low power management for a portable computer that powers down various sections of the computer when they are not used.
U.S. Pat. No. 5,598,566 issued Jan. 28, 1997 to Pascucci et al. entitled NETWORKED FACILITIES MANAGEMENT SYSTEM HAVING A NODE CONFIGURED WITH DISTRIBUTED LOAD MANAGEMENT SOFTWARE TO MANIPULATE LOADS CONTROLLED BY OTHER NODES discloses a networked system applicable for facilities management that limits energy consumption using stored restoration characteristics of loads controlled by nodes.
U.S. Pat. No. 5,623,677 issued Apr. 22, 1996 to Townsley et al. entitled APPARATUS AND METHOD FOR REDUCING POWER CONSUMPTION A COMPUTER SYSTEM discloses a method and apparatus for reducing power consumption in a computer system where a program is used to determine when the processor is in an inactive state to cause clocking signals and the power supply to be disabled.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a power reduction means for a processor including a microcode decoder unit for receiving and decoding microinstructions and generating decode data in response to the microinstructions.
Another object of the present invention is to provide a power reduction means for a processor including a microcode decode unit for generating decode data and a plurality of latches for receiving the decode data.
Still another object of the present invention is to provide a processor further including a clock gate control unit for receiving microinstructions simultaneously with a decode unit and coupled to a plurality of latches for controllably clocking the latches.
A still further object of the present invention is to provide a power reduction means for a processor to reduce power while the processor is executing application code.
Other features, advantages and benefits of the present invention will become apparent in the following description taken in conjunction with the following drawings. It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory but are not to be restrictive of the invention. The accompanying drawings which are incorporated in and constitute a part of this invention and, together with the description, serve to explain the principles of the invention in general terms. Like numerals refer to like parts throughout the disclosure.
REFERENCES:
patent: 4615005 (1986-09-01), Maejima et al.
patent: 5220672 (1993-06-01), Nakao et al.
patent: 5396634 (1995-03-01), Zaidi et al.
patent: 5428790 (1995-06-01), Harper et al.
patent: 5557557 (1996-09-01), Frantz et al.
patent: 5560024 (1996-09-01), Harper et al.
patent: 5598566 (1997-01-01), Pascucci et al.
patent: 5623677 (1997-04-01), Townsley et al.
patent: 5675808 (1997-10-01), Gulick et al.
patent: 5740411 (1998-04-01), Hearn et al.
patent: 5826053 (1998-10-01), Witt
patent: 5964884 (1999-10-01), Partovi et al.
patent: 5970235 (1999-10-01), Witt et al.
patent: 5974505 (1999-10-01), Kuttanna et al.
Moore William P.
Ventrone Sebastian T.
Chen Te Yu
Goodwin John J.
International Business Machines - Corporation
Pan Daniel H.
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