Apparatus and method for reducing power consumption in...

Details Apparatus and method for reducing power consumption in... Apparatus and method for reducing power consumption in...

2006-02-27

2008-10-14

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Computer power control

Power conservation

C326S039000, C326S041000, C713S601000

Reexamination Certificate

active

07437584

ABSTRACT:
An apparatus and method for reducing power consumption in a programmable logic device (PLOD) having multiple logic blocks and macrocells. Power consumption is reduced by detecting programmable switch values in each macrocell and generating a clock control signal based on the switch values. The clock control signal controls a macrocell buffer used for compensating for distortion of clock signals inputted to the macrocell. The macrocell buffer is disabled if the clock signals are not being used by the corresponding macrocell, thereby preventing unnecessary toggling and power consumption.

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