Apparatus and method for reducing LDRQ input pin count of a...

Details Apparatus and method for reducing LDRQ input pin count of a... Apparatus and method for reducing LDRQ input pin count of a...

2006-04-11

2006-04-11

Perveen, Rehana (Department: 2111)

Electrical computers and digital data processing systems: input/

Access arbitrating

C710S244000, C710S024000

Reexamination Certificate

active

07028120

ABSTRACT:
An apparatus and method for reducing LDRQ input pin count of a low pin count (LPC) host are provided. The LPC host is series of connecting with a plurality of peripheral devices, the peripheral device having a LDRQ control device within. The LDRQ control device comprises a LDRQ to DRQ decoder, a DRQ arbiter, and a DRQ to LDRQ encoder. In the LDRQ control device, a LDRQ signal is decoded into a DRQ signal via the LDRQ to DRQ decoder and then the DRQ signal is priority arbitrated via the DRQ arbiter. Next, the arbitrated DRQ signal is transferred into a LDRQ signal via DRQ to LDRQ encoder. Following, the LDRQ signal is outputted into the next stage peripheral device or to output into a LDRQ input pin of the LPC host, so as the LPC host only need one LDRQ input pin for purposing to effectively reduce the LDRQ input pin count and lower the manufacturing cost of the LPC host.

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