Apparatus and method for reducing drain modulation of high...

Details Apparatus and method for reducing drain modulation of high... Apparatus and method for reducing drain modulation of high...

2008-07-15

2008-07-15

Choe, Henry K (Department: 2817)

Amplifiers

With semiconductor amplifying device

Including particular biasing arrangement

C330S285000

Reexamination Certificate

active

07400201

ABSTRACT:
An apparatus and a method for reducing drain modulation in a high power amplifier are provided, in which an adder supplies a current corresponding to a voltage reduced by a drain modulation, and a bias unit adds the current supplied from the adder to a DC bias and supplies the added current to a drain of a transistor. Accordingly, the drain modulation occurring in the transistor can be minimized and an output characteristic of the high power transistor can be improved.

REFERENCES:
patent: 3984783 (1976-10-01), Bickley
patent: 6111466 (2000-08-01), Mokhtar et al.
patent: 6437646 (2002-08-01), Masahiro
patent: 6657498 (2003-12-01), Park et al.
patent: 7315211 (2008-01-01), Lee et al.

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