Apparatus and method for reducing data bus pin count of an inter

Details Apparatus and method for reducing data bus pin count of an inter Apparatus and method for reducing data bus pin count of an inter

1997-06-17

2000-07-25

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711122, 711140, 711167, 710126, 710127, 710129, G06F 1200, G06F 1314

Patent

active

06094711&

ABSTRACT:
The pin count of a processor is substantially reduced while effectively maintaining processor performance by using a staging register to receive and store a first data segment from a bus. A second data segment is received from the bus in a subsequent bus cycle and loaded into a cache. A steering circuit dynamically selects the transfer of the first or the second segment to a processor core, and orders positioning of the first and second data segments into the cache. In some embodiments, the cache is a first level cache and a second level cache is inserted between the bus and the processor. In these embodiments, the processor includes a bypassing circuit for designating the ordering of bus data in response to a memory access that misses the first level cache and hits the second level cache.

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