Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-05-18
2001-03-20
Nelms, David (Department: 2818)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C327S108000
Reexamination Certificate
active
06204683
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of signal transmission lines implemented in a semiconductor device that includes an integrated circuit or chip. More specifically, the invention relates to the field of data signal loss due to the physical structures of signal lines and busses in integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuit technology has continually advanced to produce increased device performance largely by shrinking the dimensions of the physical structures fabricated on semiconductor chips. For example, the trend today is to produce devices in signal lines having physical dimensions in the sub-micron range.
As structures have been scaled down in size, factors such as noise and signal interference have become major problems. Basically, the close physical distance between adjacent bidirectional signal lines leads to unintentional coupling and interference. This problem is commonly referred to as crosstalk.
A variety of techniques have been used to reduce crosstalk between adjacent signal lines. In the field of random access memory arrays, shielded bit line architectures have been employed in which two pairs of opposed bit lines associated with a common sense amplifier have an adjacent unselected line pair that is clamped to AC ground to shield the selected line pair from dynamic coupling effects. This approach is described in U.S. Pat. No. 5,010,524. A similar approach is disclosed in U.S. Pat. No. 5,646,556, which teaches an apparatus for precharging pairs of bus conductors to alternating rails in order to minimize crosstalk and speed degradation problems. Another example of modifying the spacing and physical arrangement of the signal lines to prevent crosstalk is described in U.S. Pat. No. 5,475,643.
Other practitioners have approached the problem from a different perspective. For example, U.S. Pat. No. 5,596,506 teaches a method for predicting respective magnitudes of crosstalk voltages before the actual fabrication of an integrated circuit (I/C) chip. Following circuit simulation, the signal line layout of the chip is modified according to an algorithm, which includes changing driver circuits, moving signal lines, and inserting buffer circuits into the chip. U.S. Pat. No. 5,311,074 attempts a more radical approach to reducing crosstalk by reducing signal line voltages through a large scale cell array region of the chip. The signal voltages are restored back to their original logic levels upon exiting the cell array.
Because digital busses typically consist of numerous transmission lines routed in close proximity to each other—with the individual signal lines providing bi-directional transmission capabilities—one of the effects of coupling is an electrical change in the impedance of the transmission line due to the state of neighboring transmission lines. By way of example, coupled transmission lines have various orthogonal impedance modes that can be used in superposition to describe any set of bus states. For a N conductor coupled bus, there are N different modes. Each of these N modes has an associated impedance that is commonly referred to as the modal impedance.
Any given state of the digital bus causes a member transmission line to have an effective electrical impedance that is a combination of the modal impedances. This effective electrical impedance is always greater than or equal to the lowest modal impedance. Similarly, the effective electrical impedance is always less than or equal to the largest modal impedance. In the context of the present application, the effective electrical impedance of a transmission line is referred to as the crosstalk induced impedance. Thus, crosstalk induced impedances are state dependent impedances.
In a high performance, bidirectional digital bus implemented with CMOS circuit technology, it is important to match the driver impedance to the transmission line impedance in order to obtain good signal quality, and also to reduce inter-symbol interference (ISI). Inter-symbol interference refers to the timing and signal quality impact of the previous state of the transmission line on the current state. In CMOS and other types of bidirectional busses, ISI is a function of the mismatch between the driver impedance, the transmission line impedance, and the transmission line length. Most often, it is impractical to reduce the transmission line length. Therefore it is crucial to match the driver impedance to the line impedance as closely as possible to reduce ISI and to obtain acceptable signal quality. However, an unfulfilled need exists for an apparatus and method capable of compensating for the differences in crosstalk induced impedances for coupled busses.
SUMMARY OF THE INVENTION
The present invention is useful in reducing the maximum current demand of bus drivers in an integrated circuit and may be advantageously employed to achieve a higher routing density of bus lines while still maintaining acceptable signal quality and ISI. The invention provides a way to compensate for variations in crosstalk induced impedances in integrated circuits implementing coupled signal busses.
In one embodiment, the invention provides an apparatus for driving a digital bus having a plurality of transmission lines. The apparatus includes a plurality of transistors coupled to an output node, which is connected to a transmission line of the digital bus. Control circuitry selectively enables/disables each of the transistors to create a transistor combination to produce an impedance at the output node that matches the effective electrical impedance of the digital bus.
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Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Lam David
Nelms David
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