Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate
2011-05-10
2011-05-10
Chase, Shelly A (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Error/fault detection technique
Reexamination Certificate
active
07941736
ABSTRACT:
Disclosed is an apparatus for receiving a signal in a communication system, which receives the signal, and decodes the received signal in a non-binary Low Density Parity Check (LDPC) decoding scheme, in which elements of a Galois field are expressed by an exponent representation, thereby minimizing the memory capacity required for a check node operation when the non-binary LDPC code is decoded.
REFERENCES:
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patent: WO 2005/020500 (2005-03-01), None
patent: WO 2005/062472 (2005-07-01), None
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Kim Jae-Yoel
Lestable Thierry
Lim Chi-Woo
Park Dong-seek
Park Sung-Eun
Chase Shelly A
Samsung Electronics Co,. Ltd
The Farrell Law Firm P.C.
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