Apparatus and method for real time data error capture and compre

Details Apparatus and method for real time data error capture and compre Apparatus and method for real time data error capture and compre

1992-02-24

1994-05-31

Baker, Stephen M.

Excavating

371 216, G11C 2900

Patent

active

053175735

ABSTRACT:
Fail information from testing of a DUT memory array is captured and compressed by utilizing a compression matrix which is related in size to the available redundancy associated with the DUT (device under test) memory array, and which, in essence, defines the limits of redundancy repair. The compression matrix includes a plurality of matrix cells fewer in number than the number of memory cells in the DUT memory array and is arranged in a matrix of compression rows and compression columns, the number R of compression rows in the compression matrix being equal to (a predetermined number of redundant rows in the memory array) times (a predetermined number of redundant memory columns+1), and the number C of compression columns in the compression matrix being equal to (a predetermined number of redundant memory columns) times (a predetermined number of redundant memory rows+1). The compression matrix is loaded with the fail information concurrently with testing of the DUT memory array.

REFERENCES:
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patent: 4628509 (1986-12-01), Kawaguchi
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Tarr, M., "Defect Analysis System Speeds Test and Repair of Redundant Memories", Electronics, Jan. 12, 1984, pp. 175-179.
IBM Technical Disclosure Bulletin, vol. 29, No. 6, Nov. 1986, "Best Solution Generator For Redundancy", pp. 2756-2758.

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