Apparatus and method for read-accessing write-only registers in

Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories

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711154, G06F 1310

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active

058929770

ABSTRACT:
A computer system has an I/O address space with an ISA bus, and a configuration address space with a PCI bus, further the system including an ISA DMA (Direct Memory Access) controller with two or more DMA channels on the ISA bus, an I/O register implemented in the DMA controller for storing information for DMA transfer on each of the DMA channels, and a register control logic device for controlling read/write-access to the I/O register. The I/O registers are allocated to the I/O address space, and further write-only registers in the I/O registers are allocated to the configuration address space. When a HOST-PCI bridge device generates a configuration read cycle through the configuration address space on the PCI bus, the register control logic device read-accesses the write-only registers, in response to the generated configuration read cycle.

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PCI Local Bus Specification, PCI Special Interest Group, Revision 2.1, Jun. 1, 1995.
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Mobile PC/PCI DMA Arbitration and Protocols: MHPG Architecture Functional Architecture Specification, Intel Corporation, Revision 2.2, Apr. 22, 1996 .

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