Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
2001-10-27
2004-09-28
Auve, Glenn A. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S104000, C710S117000, C710S268000
Reexamination Certificate
active
06799234
ABSTRACT:
BACKGROUND OF THE INVENTION
Cards inserted in devices utilizing a PCI backplane, for example in routers, must be configured and assigned specific resources in the backplane such as “ID select” lines, IRQs, memory regions, and DMA channels.
In all PCI devices using a PCI bus various means have been devised to solve this problem.
In some architectures, the problem is solved by having an “additional” bus in parallel to the PCI bus. For example, this additional bus may be a Serial Peripheral Interface (SPI) bus which is a serial bus for eight and sixteen bit data transfer operations. There are separate data lines for transmission and reception and a device coupled to the bus may be a transmitter or a receiver. The devices connected to the SPI bus may be classified as Master or Slave. A Master device initiates an information transfer on the bus and generates clock and control signals. A Slave device is controlled by a Master through a slave select (chip enable) line. Generally, a dedicated select line is required for each slave device.
In such architectures, each inserted card is assigned an SPI bus chip select line by its physical placement in a router. A protocol implemented on the SPI bus is then used to discover and assign the cards to specific PCI resources. This technique has the disadvantage that it requires an additional bus to do the discovery and assignment of cards on the PCI back plane.
In the PC104+ standard (which is a small form factor stackable PC architecture), PCI resources are assigned with a rotary switch or dipswitch on each daughter card. For example, if four cards are stacked then the stack shares four IDSEL lines, 3 pairs of GNT/REQ lines (modules
3
and
4
share one pair of GNT/REQ lines) and a pair of INTA, INTB, INTC, and INTD lines. The rotary switches on each of the stacked modules control multiplexers that assign specific lines to specific ones of the stacked modules. This is problematic because manual configuration errors may arise and can cause the whole system to malfunction. It also requires manual actions to deploy the cards properly.
In the PC104+ form factor, card space is at a premium, therefore using the technique of having a “parallel” bus to the PCI bus is expensive. Doing so would consume a great deal of additional board space for the stackable headers.
Accordingly, a new approach to “automatically” discover and assign PCI resources to cards inserted into backplane slots, such as PC104+ cards, that doesn't consume scarce resources, such as card space, is needed.
BRIEF SUMMARY OF THE INVENTION
According to one aspect of the invention, cards inserted into a PCI backplane are “automatically” assigned to resources on the PCI bus.
According to another aspect of the invention, automatic rather than manual resource allocation is implemented without requiring the addition of another bus in parallel with the PCI back plane to assign PCI resources.
According to another aspect of the invention, a multiplexer control bus utilizes existing pairs of bus lines in the PCI backplane as bus lines. The multiplexer control bus is a time division multiplexed bus with time slots aggregated into frames. Thus, no additional bus lines and card space are required to automatically configure and assign bus resources to the slave devices.
According to another aspect of the invention, the multiplexer control bus utilizes the PCI GNT/REQ lines as bus lines.
According to another aspect of the invention, the slave device selects slots based on a random delay number based on the time of charging of a low precision charging circuit.
According to another aspect of the invention, if two slave devices select the same time slot the master device asserts a reset signal.
According to another aspect of the invention, if two or more slave devices generate the same random delay number then a counting circuit is adjusted to more accurately measure the charging interval.
Other features and advantages of the invention will be apparent in view of the following detailed description and appended drawings.
REFERENCES:
patent: 5758171 (1998-05-01), Ramamurthy et al.
patent: 6055598 (2000-04-01), Lange
patent: 6457069 (2002-09-01), Stanley
PC/104—Plus Specification, Version 1.0, Feb. 1997, PCI Special Interest Group, P.O. Box 14070, Portland, OR 97214.
Ohio State University, “The Serial Peripheral Interface [subtitled] Nautilus Chip—Project DEEPSEA (Digital Exportation of an Established Protocol from Sensing Encoded Analog)” [online], Jan. 7, 2001, retrieved from the internet on Sep. 5, 2001: <URL:http://eewww.eng.ohio-state.edu/ie/main/current_research/SPI_Nautilus_chip/>.
Moon Billy Gayle
Schnell Mark
Auve Glenn A.
Cisco Technology Inc.
Krueger Charles E.
Lee Christopher E.
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