Static information storage and retrieval – Systems using particular element – Capacitors
Reexamination Certificate
2001-06-28
2003-04-01
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Systems using particular element
Capacitors
C365S189110
Reexamination Certificate
active
06542399
ABSTRACT:
TECHNICAL FIELD
The present invention relates to memory and, in particular, to an apparatus and method for pumping memory cells in a memory.
BACKGROUND
In dynamic random access memories (DRAM), densities are increasing and operating voltages are decreasing. In addition, DRAMs are now being embedded with other logic and functionality on a single integrated circuit (IC). The technological drive toward higher densities, lower operating voltages and embeddedness for DRAMs are all contributing to a decreasing differential signal voltage (related to noise margin) detected on the bit lines during the read operation of a memory cell.
One apparatus and method of pumping memory cells is described in U.S. application Ser. No. 09/751,367 having a filing date of Dec. 29, 2000 and is incorporated herein by reference.
Accordingly, there exists a need for a method and apparatus for increasing the differential signal voltage detected during a read operation on the bit lines of a memory without the need for additional complex circuitry.
SUMMARY OF THE INVENTION
According to the present invention, there is provided a memory having a first bit line and a second bit line, with each bit line having a charge-storing element having a first plate and a second plate coupled thereto through an access device controlled by a respective word line. A voltage driver circuit, having a first output terminal coupled to the second plates of the first and second charge-storing elements, provides a high logic level voltage to the second plate of the first charge-storing element when a low logic level is present on the first bit line, a low logic level voltage to the second plate of the first charge-storing element when a high logic level voltage is present on the first bit line, and substantially the same voltage as an intermediate voltage to the second plate of the first charge-storing element when the intermediate voltage level is present on the first bit line.
In another embodiment of the present invention, there is provided a memory having a first bit line (true), a first charge-storing element having a first plate and a second plate, and a first access device having a first end, a second end and a control terminal, with the first end coupled to the first bit line, the second end coupled to the first plate of the first charge-storing element and defining a first node, and the control terminal coupled to a first word line. The memory also includes a second bit line (complement), a second charge-storing element having a first plate and a second plate, and a second access device with the first end, a second end and a control terminal, the first end coupled to the second bit line, the second end coupled to the first plate of the second charge-storing element and defining a second node, and the control terminal coupled to a second word line. A voltage driver circuit, having a first input terminal and an output terminal coupled to the second plates of the first and second charge-storing elements, applies a first voltage to the second plates when either one of the first or second access devices is activated and a second voltage is applied to the respective node, and also applies a third voltage to the second plates after the respective activated access device is deactivated.
In another embodiment of the present invention, there is provided a method of pumping a memory by activating a first word line for coupling a first plate of a first memory cell to a first bit line, activating a sense amplifier coupled to the first bit line and a second bit line for detecting a voltage differential between the first bit line and the second bit line, applying a high logic voltage value to the first bit line and a low logic voltage value to the second bit line, applying a first voltage to a second plate of the first memory cell and a second plate of a second memory cell, the second memory cell associated with the second bit line deactivating the first word line for decoupling the first plate of the first memory cell from the first bit line, and after the step of deactivating the first word line, applying a second voltage to the second plates of the first and second memory cells wherein the second voltage is greater than the first voltage.
In yet another embodiment of the present invention, there is provided a method of pumping a memory by precharging and equilibrating a first bit line (true) and a second bit line (complement) to an intermediate voltage, the intermediate voltage having a magnitude between a first voltage and a second voltage representing a logic high and a logic low, respectively, activating a first word line for coupling a first plate of a first memory cell to the first bit line, activating a sense amplifier coupled to the first bit line and the second bit line, applying the first voltage to the first bit line and the second voltage to the second bit line, applying the second voltage to a second plate of the first memory cell and a second plate of a second memory cell, the second memory cell associated with the second bit line and a second word line, deactivating the first word line for decoupling the first plate of the first memory cell from the first bit line, and after the step of deactivating the first word line, applying a third voltage to the second plates of the first and second memory cells, wherein the third voltage is substantially equal to the intermediate voltage.
REFERENCES:
patent: 4769784 (1988-09-01), Doluca et al.
patent: 5255232 (1993-10-01), Foss et al.
patent: 5303183 (1994-04-01), Asakura
patent: 5414656 (1995-05-01), Kenney
patent: 5508962 (1996-04-01), McLaughlin et al.
patent: 5734603 (1998-03-01), Tai
patent: 6081459 (2000-06-01), Kim
patent: 6147896 (2000-11-01), Kim et al.
patent: 6236598 (2001-05-01), Chou
Kazuyasu Fujishima, et al., “A Storage-Node Boosted RAM with Word-Line Delay Compensation”, IEEE Journal of Solid-State Circuits, vol. SC-17, No. 5, Oct. 1982, pp. 872-876.
Mikio Asakura, Kazutami Arimoto, “Cell-Plate Line Connecting Complementary Bit-Line (C3) Architecture for Battery-Operating DRAM's”, IEEE Journal of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, pp. 597-602.
Jorgenson Lisa K.
Munck William A.
Nguyen Tan T.
STMicroelectronics Inc.
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