Apparatus and method for providing non-blocking pipelined cache

Details Apparatus and method for providing non-blocking pipelined cache Apparatus and method for providing non-blocking pipelined cache

1997-06-05

2000-07-04

Cabeca, John W.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711141, 711145, 711118, 711169, 711144, G06F 1208

Patent

active

060852925

ABSTRACT:
A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A memory controller receives the missed addresses from the address queue. A data queue receives data stored at the missed addresses from the memory controller. A probe result queue is connected to the address cache for storing data cache line addresses and hit/miss information. A multiplexer connected to the data cache, the data queue, and the probe result queue selects output data from the data cache or the data queue depending on the hit/miss information.

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