Apparatus and method for providing multiple channel clock-data a

Details Apparatus and method for providing multiple channel clock-data a Apparatus and method for providing multiple channel clock-data a

1996-08-07

1999-07-06

Gossage, Glenn

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711109, 395558, 370464, 370516, 370536, G06P 1300, H04J 306

Patent

active

059208970

ABSTRACT:
An apparatus and method for aligning any number of multiple parallel channels of data signals according to a single clock is provided. The synchronization process is accomplished through the use of a First-In-First-Out (FIFO) principle and individual storage elements implementing the FIFO principle for each received data channel. Each channel's data signals are read into a corresponding storage element, maintained in order, and read out upon the assertion of read signals in synchronization with a designated single clock signal. The apparatus and method preferably uses indications of data ready to be read from a storage element implementing the FIFO principle and the presence of a master clock signal to activate the reading of the data from the corresponding storage element. Therefore, each data channel is fully aligned with the master clock signal. The clock-data alignment function may be implemented for a 100BASE-T4 receiver.

REFERENCES:
patent: 4984251 (1991-01-01), Perloff
patent: 5251210 (1993-10-01), Mann et al.
Fast Ethernet Alliance, "Presentation Reprints", IEEE 802.3u, Mar. 7, 1994.
Supplement to IEEE Standard 802.3, 100BASE-T, 802.3u/D5.3, Jun. 12, 1995, pp. 59-138.
J. Scott Gardner, "Designing with the IDT SyncFIFO .TM.: The Architecture of the Future", Application Note AN-60 (Integrated Device Technology, Inc.), pp. 1-12.
"10/100 Base-T4 Fast-.PHI..TM. Transceiver", BCM5000-SP9 (Broadcom Corporation), Apr. 2, 1996, pp. 1-38.
"100Base-T4/10BASE-T Fast Ethernet Transceiver (CAT3)", Doc. No. 38-00415 (Cypress-CY7C971), pp. 7-42 to 7-65.
"10Mbps/100Mbps Lan Physical Layer Interface", (Intel-82553), pp. 1-60.

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