Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-04-21
2002-04-09
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C712S227000
Reexamination Certificate
active
06370660
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to debugging a computer system and software functions associated therewith.
2. Description of the Related Art
The time and cost of developing and debugging new hardware and software products is a significant factor in product development. A capable and cost efficient debug environment can decrease the cost and time to bring a new product to market. The need to provide software debug support is particularly acute within the embedded products industry, where specialized on-chip circuitry is often combined with a processor core.
Logic analyzers, read-only memory (ROM) emulators and in-circuit emulators (ICE) have commonly been used to help provide debug support. In-circuit emulators do provide certain advantages over other debug environments, offering complete control and visibility over memory and register contents, as well as overlay and trace memory in case system memory is insufficient. Use of traditional in-circuit emulators, which involves interfacing a custom emulator back-end with a processor socket to allow communication between emulation equipment and the target system, is becoming increasingly difficult and expensive in today's age of exotic packages and shrinking product life cycles.
A variety of hardware solutions with varying on-chip debug capability through various debug ports are being provided by the various processor manufacturers. Some advanced processors multiplex debug pins in time. In such processors, the address bus is used to report software trace information during a BTA-(Branch Target Address) cycle.
A common approach is to use a serial interface such as provided by IEEE 1149.1 (Joint Test Action Group (JTAG)), for providing debug support. In such an approach, the debug hardware provided on chip communicates with a host debug computer through the JTAG port.
In the “background Debug Mode” by Motorola, Inc. limited on-chip debug circuitry is provided for basic run control. Through a dedicated serial link requiring additional pins, a debugger can start and stop the target system and apply basic code breakpoints by inserting special instructions in system memory. Once halted, special commands are used to inspect memory variables and register contents.
Thus, the debug tool manufacturers are faced with a wide variety of processor and hardware debug approaches that they are required to support. Typically a common core debug capability is shared among the various approaches, particularly among product offerings from the same manufacturer. For instance, many debug tools support the capability to start and stop the processor, read and write to various storage locations within the processor and/or target system and to set breakpoints. However, every time a new or modified debug port is provided on a processor, new software has to be generated by the debug tool vendors to support the new or modified ports. It would be desirable to limit the amount of new software that has to be generated by the debug tool vendors in response to enhancements or changes to debug hardware on target microprocessors. In addition, it would be desirable to standardize software interfaces as much as possible in order to help achieve that goal.
SUMMARY OF THE INVENTION
Accordingly, the invention provides for a standard procedural interface operating on a host computer. In one embodiment the invention provides a host computer system for operating in a debug environment that includes a target computer system coupled to the host computer system. The host computer system includes a status register which can be interrogated. A programming interface encoded in computer readable media and executable on the host computer system, provides at least one callable function that determines whether a value of a selected bit or bits of the status register have changed from a predetermined state. The called function returns to a calling function in response to the change in value of the selected bit or bits. Otherwise, the called function waits for the change in value of the bit(s). In one embodiment, the status register includes at least one status bit that indicates a state of the target computer system and a status bit that indicates a state of the host computer system.
In another embodiment, the invention provides a method for detecting and indicating a status in a computer system debug environment that includes a target computer system and a host computer system. The method includes calling a function on the host computer. The function evaluates whether a state represented in a status register in the host computer has changed from a predetermined state. If the state represented in the status register has changed from the predetermined state, the method returns from the called function and if not, the function waits for the change in state.
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Programmer Reference, “TLA Programmatic Interface (TPI)/TLA 700 Series Logic Analyzer”, Tektronix, Inc., Wilsonville, OR, pp. 1-120 (admitted prior to Apr. 21, 1999).
Advanced Micro Devices , Inc.
Iqbal Nadeem
Zagorin O'Brien & Graham LLP
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