Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-02-23
2001-01-16
Chung, Phung M. (Department: 2785)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C365S185030
Reexamination Certificate
active
06175937
ABSTRACT:
TECHNICAL FIELD
The present invention relates to multistate memory devices, and more specifically, to an apparatus and method for programming such devices and verifying the programmed data.
BACKGROUND OF THE INVENTION
In conventional single-bit per cell memory devices, the memory cell assumes one of two information storage states, either an “on” state or an “off” state. The binary condition of “on” or “off” defines one bit of information. As a result, a memory device capable of storing n-bits of data requires (n) separate memory cells.
Increasing the number of bits which can be stored using single-bit per cell memory devices depends upon increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory bits stored in a memory device composed of single-bit capacity cells have relied upon techniques such as manufacturing larger die which contain more memory cells, or using improved photolithography techniques to build smaller memory cells. This is effective because reducing the size of a memory cell allows more cells to be placed on a given area of a single die.
An alternative to single-bit per cell designs is the storage of multiple-bits of data in a single memory cell. One type of memory in which this approach has been followed is an electrically erasable and programmable device known as a flash memory cell. In flash cells, programming is carried out by applying appropriate voltages to the source, drain, and control gate of the device for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate in order to cause the device to conduct current between the source and drain regions. This voltage is termed the threshold voltage, V
th
, of the cell. Conduction represents an “on” or erased state of the device and corresponds to a logic value of one. An “off” or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at the given set of applied voltages, the state of the cell (programmed or erased) can be found.
A multi-bit or multistate flash memory cell is produced by creating multiple, distinct threshold voltage levels within the device. Each distinct threshold voltage corresponds to a value of a set of data bits, with the number of bits representing the amount of data which can be stored in the multistate cell. This method allows multiple bits of binary data to be stored within the same memory cell. When reading the state of the memory cell, the threshold voltage value or range of values for which the memory cell conducts current (as determined by comparison with a sense amplifier having a preselected reference value) corresponds to a binary decoded value representing the programmed data. The threshold voltage level for which the cell conducts thus corresponds to a bit set representing the data programmed into the cell. Proper data storage requires that the multiple threshold voltage levels of a memory cell be separated from each other by a sufficient amount so that a level of a cell can be programmed or erased in an unambiguous manner. The relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells.
In programming a multistate memory cell, the objective is to apply a programming voltage over a proper time period to store enough charge in the floating gate to move the threshold voltage of the cell to a desired level. This level represents a state of the cell corresponding to an encoding of the data which is to be programmed into the cell. One method of programming such memory cells is to send digital data corresponding to the number of bits which can be programmed into a memory cell to the cell where it is encoded to determine the threshold voltage level which is to be set for that cell during a programming operation. The state machine for the memory system would then control the programming and data verification for each bit. Although this method can be used to program multistate memory cells, it is inefficient and not cost-effective because the programming and encoding logic must be duplicated for each block of memory cells.
U.S. Pat. No. 5,043,940, entitled “Flash EEPROM Memory Systems Having Multistate Storage Cells”, issued Aug. 27, 1991, describes a method of programming a multistate memory cell in which an iterative read-compare-program cycle is executed. During the cycle, the data intended to be programmed into a memory cell is input to a comparator, along with the outputs from a set of sense amplifiers (each having a different reference voltage) connected to the cell. The output of the sense amplifiers indicates the threshold voltage level to which the cell is programmed. If the programmed threshold voltage level corresponds to the encoded representation of the intended data, then the cell is in the correct state.
If the intended data doesn't correspond to the programmed threshold voltage level, then a programming control circuit is activated. A single, short duration programming pulse is then applied to the cell, followed by another read operation using the sense amplifiers. This cycle is repeated until the data comparison operation indicates a correct threshold voltage level, or until the maximum number of programming pulses has been applied.
U.S. Pat. No. 5,394,362, entitled “Electrically Alterable Non-volatile Memory with N-bits per Memory cell”, issued Feb. 28, 1995, describes a similar method of programming a multistate memory cell. An iterative cycle of determining the threshold voltage level of a cell, using the threshold voltage level to determine the data contained in the cell, comparing the data programmed into the cell to data intended to be programmed, and then generating a programming pulse to alter the cell's threshold voltage level is performed. This cycle is repeated using the same period and amplitude for the programming pulse during each cycle, until the sense amplifiers indicate that the cell has been properly programmed.
What is desired is an apparatus and method for programming the memory cells contained in a multistate memory system which is more efficient and cost-effective than presently used methods.
SUMMARY OF THE INVENTION
The present invention is directed to an apparatus and method for programming a multistate memory cell which has the benefit of simplifying the memory design through a general purpose control method. The method involves a transformation of the data being programmed into the memory. Two data bits are collapsed to one data bit sent to the memory (16 data bits would be sent as 8 bits to be programmed). By performing the data bit collapsing (transformation) of 2 bits to 1 bit, the memory operation is simplified. The number of write registers is reduced in half and the memory system does not require write encoding logic; only an on/off (1/0) condition is required in the logic gating. The collapsing of the data by the controller, before transmission to the memory, also reduces the number of bits to be transmitted. This increases bus bandwidth and reduces the required transmission power. Following the transmission of data from the controller to the memory, a programming sequence is initiated on the memory by the controller (a program pulse). The program pulse is set to a short duration and voltage level and only the cells loaded with a 0 data bit are enabled to be programmed by the pulse. The amount of programming is sufficient to allow enough charge to be trapped in the floating to cause the cell to move one state level higher (one V
th
level different).
Following this progra
Chevallier Christophe J.
Lakhani Vinod
Norman Robert D.
Chung Phung M.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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