Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-08-30
2003-09-23
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C711S103000, C703S015000, C326S038000, C326S039000, C326S041000
Reexamination Certificate
active
06625796
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to techniques for configuring programmable logic devices. More particularly, this invention relates to a technique for programming a set of programmable logic devices in parallel.
BACKGROUND OF THE INVENTION
Field programmable logic devices are digital logic circuits that can be programmed to perform a variety of logical functions. A specified logical function is typically stored in a memory and is subsequently programmed into a single field programmable logic device. This prior art technique does not allow multiple programmable logic devices to be programmed from a single memory. Accordingly, it would be highly desirable to provide an improved technique wherein multiple programmable logic devices can be configured in parallel from a single memory.
SUMMARY OF THE INVENTION
The invention includes a method of configuring a set of programmable logic devices. The method includes the step of partitioning a programming file into a set of programmable logic device configurations. A set of programmable logic devices are subsequently configured, in parallel, in accordance with the set of programmable logic device configurations.
The invention also includes an electronic system with a set of programmable logic devices. A memory is connected to the set of programmable logic devices. The memory stores a set of programmable logic device configurations. A microprocessor is connected to the set of programmable logic devices and the memory. The microprocessor coordinates the routing of the set of programmable logic device configurations to the set of programmable logic devices.
The invention further includes a computer readable medium to direct a processor to function in a specified manner. A first set of instructions accesses a memory storing a set of programmable logic device configurations. A second set of instructions transfers, in parallel, the set of programmable logic device configurations to a corresponding set of programmable logic devices.
The technique of the invention significantly reduces programmable logic device configuration times. In addition, the invention supports reconfigurable digital systems.
REFERENCES:
patent: 5212652 (1993-05-01), Agrawal et al.
patent: 6052755 (2000-04-01), Terrill et al.
patent: 6112020 (2000-08-01), Wright
patent: 6134707 (2000-10-01), Herrmann et al.
Prasad Nitin
Rangasayee Krishna
Altera Corporation
Garbowski Leigh M.
Pennie & Edmonds LLP
Rossoshek Helen
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