Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-08-08
2004-11-16
Baderman, Scott (Department: 2113)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S045000
Reexamination Certificate
active
06820222
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to digital signal processing units and, more particularly, to techniques for determining the power consumption of digital signal processor units.
2. Background of the Invention
The digital signal processor and related devices have found increasing application in portable apparatus, such as cell phones, wireless internet devices, etc. The power consumption is a critical parameter in portable apparatus. The power consumption determines the size of the battery and the time between recharging the battery, key parameters in the portability of devices.
However, the power consumption parameter for the digital signal processor has several variables. The hardware implementing the device can, for example, be designed to run with minimum power expenditure. Even after every effort has been employed to reduce to power requirements of the hardware, the software programs may not be power efficient. Individual programs can be optimized to provide minimum power consumption. In addition, not only can the central processing unit draw power, but bus activity can also result in the consumption of power. However, before these parameters can be optimized, a technique for the measurement of the power consumption must be provided.
In designing and testing a central processing unit, a simulation model is provided for the proposed design. Using the simulation model, a simulation of the processing activity can be performed for the central processing unit, i.e., for a set of input signals and the set of output signals. Even the internal operation of the data processing unit can be determined from the simulation model. The simulation model allows design changes and improvements to be investigated in central processing unit without the lengthy process of fabricating the apparatus.
Referring to
FIG. 1
, a process of designing and fabricating a central processing unit is summarized. Based on a series of requirements for a central processing unit and based on characteristics of technology used in implementing a central processing unit, a simulation model is prepared in step
10
. The simulation model simulates the physical electrical parameters of a physically-implemented central processing unit. Using the simulation model, the operation of the simulation model is tested and the model is refined in step
11
. Any problems identified this stage are typically resolved in an updated simulation model. Because of the time required actually to fabricate a central processing unit, any problems that can be identified and resolved at this stage provides a big impact on the schedule for providing a functioning central processing unit. When a final version of the simulation model has been achieved, then a physical central processing unit is fabricated using the simulation model as template in step
12
. The implemented central processing unit is tested in step
13
. In step
14
, the testing of the central processing unit is examined to determine if changes are necessary to the central processing unit design and, consequently, to the simulation model. When no changes are needed, the process ends in step
16
. When changes in the central processing unit are required, the process proceeds to step
15
wherein the simulation model is modified. After the modifications are completed, the process returns to step
11
wherein the simulation model is tested and refined.
However, the simulation models have limitations that become apparent when the central processing unit is fabricated. In order to test and verify the operation of the implemented central processing unit, selected signals can be retrieved from the central processing unit and other selected signals applied to the central processing unit. By way of specific example, the JTAG (Joint Test Action Group) protocol identifies specific signals for application to the central processing unit and retrieval from the central processing unit. The purpose of this protocol is to standardize the signals for convenience in testing and debug processes. The signals of the JTAG protocol as well as trace signals can used in the testing and debug processes. The central processing unit typically has a trace port dedicated to exchange of the trace signals between selected components in the central processing unit and a trace unit. The trace unit is programmed to interpret the trace signals received from the central processing unit. While the JTAG protocol has been an improvement in the tools available to the designer and developer of both the central processing unit and the programs that control the operation of the central processing unit, recently, the number of trace signals has been greatly expanded, i.e., relative to the number of JTAG protocol signals. The additional signals have been particularly useful in obtaining information about the internal state of the central processing unit.
One of the most important applications of the data processing technology has be to battery-operated portable devices, for example, hand-held appliances. In these applications, the requirement is that the power consumption be as low as possible. The devices have been designed for minimum power operation. One further parameter in the reduction of power consumption is the program controlling the operation of the data processing unit. When initially developed, the program is typically not optimized for power consumption. However, several variations in a program may be possible when an attempt is made to reduce power consumption in a program.
A need has therefore been felt for apparatus and an associated method having the feature that the power consumption of a central processing unit of a digital signal processing system can be measured as the result of execution of a program. The apparatus and associated method would further have the feature that the power consumption of the program could be related to the individual steps in the program. The apparatus and associated method would still further have the feature the power consumed by the central processing unit can be determined for the individual clock cycles during the execution of the program.
SUMMARY OF THE INVENTION
The aforementioned and other features are accomplished, according to the present invention, by executing the activity for which power consumption is to be optimized in a central processing unit and using the signals collected from the central processing unit to execute the same activity on the simulation model. Trace components collect and store in memory the input signals to and the output signals from the central processing unit for each clock cycle. The signals collected are sufficient to recreate the activity of the central processing unit in a simulation model when the initial states are the same. The recorded set of input and output signals are applied to a simulation model of the central processing unit. The input signals and the output signals permit the state of the central processing unit to be determined for each clock cycle when applied to the simulation model from the equivalent initial state. Using the simulation model, the power dissipated for each state of the data processing unit can be determined. Therefore, using the input and output signals to determine the state of the central processing unit for each clock cycle, the total power used by the program can be calculated. By relating the power consumed as a function of the execution of the program, those portions of the program consuming the most power can be examined to determine whether the power being consumed can be minimized.
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Baderman Scott
Brady W. James
Holloway William W.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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