Apparatus and method for processing packetized information over

Details Apparatus and method for processing packetized information over Apparatus and method for processing packetized information over

1998-11-20

2000-12-05

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

370912, G06F 1300

Patent

active

061579726

ABSTRACT:
An IEEE 1394 serial bus, during bus initialization, transmits a plurality of self-ID packets across the bus. Each node on the bus is operable to receive the self-ID packet from the bus (140) via receiver (146). Asynchronous packets and isochronous packets are stored in a FIFO (166) for later use by a host interface (150). The self-ID packets are verified by a hardware circuit (170) that provides verification of the self-ID packets as they are received without requiring the software to later evaluate the self-ID packets from storage in the FIFO (166). If an error is determined, this is stored in registers (164) for later processing by the host interface (150).

REFERENCES:
patent: 5724517 (1998-03-01), Cook et al.
patent: 5764930 (1998-06-01), Staats
patent: 5919261 (1999-07-01), Aoki et al.

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