Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1996-09-12
2000-02-01
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711138, G06F 1208
Patent
active
060214678
ABSTRACT:
An apparatus and method for processing multiple cache misses to a single cache line in an information handling system which includes a miss queue for storing requests for data not located in a level one cache and a comparator for comparing requests for data stored in the miss queue to determine if there are multiple requests for data located in the same cache line of a level two cache. Each new request for data from the same cache line of the level two cache as an older original request for data in the miss queue is marked as a load hit reload. The requests marked as load hit reloads are then grouped together with the matching original request and forwarded together to the level two cache wherein the original request requests the data from level two cache. The load hit reload requests do not access level two cache but instead bypass access of level two cache by extracting data from the cache line outputted from level two cache for the matching original request. The present invention reduces the number of accesses to the level two cache and allows data requests to be satisfied in parallel versus serially when multiple successive level one cache misses occur.
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Konigsburg Brian R.
Muhich John Stephen
Thatcher Larry Edward
White Steven Wayne
Chan Eddie P.
Dillon Andrew J.
England Anthony V.S.
International Business Machines - Corporation
Portka Gary J.
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