Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2001-02-08
2004-04-13
Iqbal, Nadeem (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S817000
Reexamination Certificate
active
06721903
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to an information processor like a microcomputer, and more particularly relates to a microcomputer that can continuously perform a set of predetermined processing almost as intended without suspending it even if the computer has received noise at its power supply terminal, for example.
In a conventional microcomputer in general, when a runaway is caused in the microcomputer due to extraneously incoming noise, a watchdog timer finds the runaway to make the microcomputer return to its normal operation mode by resetting it. Alternatively, in a situation where the clock should not be reset, for example, the microcomputer is not reset but is made to enter a standby mode and wait for the user's key input. Also, according to a technique disclosed in Japanese Laid-Open Publication No. 61-67119, even if the presence of extraneous noise at a power supply terminal is found and data has been destroyed by the noise, the data is reconstructed to avoid serious malfunction.
In the prior art, however, if the presence of extraneous noise is detected, the microcomputer should be either reset or made to enter a standby mode to suspend a set of predetermined processing. Thus, the processing is suspended as it is when the noise enters. In addition, according to the technique disclosed in the above-identified publication, before the noise is detected, a malfunction may already have been caused within the microcomputer. Accordingly, even if the data is reconstructed, it might be impossible in such a situation to continue the predetermined process as intended. For example, suppose a conventional microcomputer has been instructed to automatically finish a “cooking” operation by a prescribed time. In accordance with the instruction, the computer starts “cooking” automatically. But when noise is detected, the “cooking” operation must be suspended halfway or a malfunction may have been caused. Thus, the “cooking” operation may not be finished as expected.
SUMMARY OF THE INVENTION
An object of the present invention is having a set of predetermined processing or its equivalent operation performed continuously, or without being suspended, by a microcomputer even if noise is detected at a power supply terminal of the microcomputer while the processing is being executed.
To achieve this object, according to the present invention, while extraneously incoming noise is still lower than a predetermined level, important information indispensable for a predetermined process is protected. At a point in time that the noise has increased to such a level as causing any malfunction, the CPU is suspended to avoid a runaway of the CPU. And if the noise has decreased from the predetermined level, the CPU is rebooted to continue the predetermined process in accordance with the correct information protected.
An inventive information processor is programmed to continuously perform a predetermined process using a CPU even if extraneous noise has been detected at the processor. While the noise is lower than a predetermined level, information needed for the predetermined process is protected. If the noise increases to exceed the predetermined level, the CPU is suspended. On the other hand, if the noise decreases from the predetermined level, the CPU is rebooted in accordance with the protected information.
Another inventive information processor is so constructed as to perform a predetermined process. The processor includes: a CPU; storage means; noise detecting means for measuring extraneous noise by first and second reference levels, the second level being higher than the first level; write-protect means for saving important information, indispensable for continuing the predetermined process, on the storage means and protecting the information as non-rewritable if the noise detecting means has detected the noise at the first reference level while the predetermined process is being performed; suspension control means for getting the predetermined process suspended by the CPU at a point in time that the noise detecting means has detected the noise at the second reference level while the predetermined process is being performed; and resumption control means for getting the predetermined process resumed in accordance with the important information that has been saved by the write-protect means when the noise detecting means finds the detected noise lower than the first reference level while the predetermined process is being suspended.
In this particular embodiment, the first reference level is either a predetermined lower level or a predetermined higher level. When the noise detecting means detects the noise at the lower level, the write-protect means saves important information, which determines a state of the CPU, as non-rewritable information on the storage means. And when the noise detecting means detects the noise at the higher level, the write-protect means saves another important information, which represents a status of the predetermined process, as another non-rewritable information on the storage means. And when the noise detecting means finds the detected noise lower than the lower level, the resumption control means gets the predetermined process resumed in accordance with the important information that has been saved by the write-protect means and that determines the state of the CPU and represents the status of the predetermined process.
More specifically, the resumption control means receives an output of the noise detecting means. When the noise detecting means finds the detected noise lower than the first reference level, the resumption control means makes the important information, which has been saved by the write-protect means, rewritable in response to the output of the noise detecting means.
Alternatively, the resumption control means gets the predetermined process resumed in accordance with the important information that has been saved by the write-protect means and a version of the information while the predetermined process is being suspended.
As another alternative, the resumption control means gets the predetermined process resumed in accordance with the important information that has been saved by the write-protect means and a version of the information at the time that the predetermined process is resumed.
In still another embodiment, before resuming the predetermined process, the resumption control means performs a special preprocess different from the predetermined process.
In yet another embodiment, the CPU operates responsive to a clock signal supplied at a frequency. The processor further includes frequency dividing means for dividing the frequency of the clock signal and delivering the clock signal with the divided frequency to the CPU when the noise detecting means detects the noise at the first reference level while the predetermined process is being performed.
In still another embodiment, the processor further includes continuing means for performing a simplified version of the predetermined process when the noise detecting means detects the noise at the first reference level while the predetermined process is being performed.
In still another embodiment, the noise detecting means includes: voltage generating means for generating a predetermined voltage at a voltage generating node; and an n-channel transistor including source, drain and gate terminals. The source terminal is grounded. The drain terminal functions as an output terminal for a noise detection signal. And the gate terminal receives the predetermined voltage that has been generated by the voltage generating means. The noise detecting means further includes initializing means for initializing a voltage at the output terminal to H level.
In this particular embodiment, the voltage generating means includes: a first resistor and a capacitor that are both connected to a power supply and to the voltage generating node; and a second resistor connected to a line with a potential lower than a ground potential and to the voltage generating node.
In still another embod
Matsumoto Masahiko
Satoh Shigenori
Yoshioka Shiro
Iqbal Nadeem
McCarthy Christopher S.
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