Apparatus and method for processing a sequence of jump...

Electrical computers and digital processing systems: processing – Processing control – Branching

Reexamination Certificate

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C712S202000, C712S245000

Reexamination Certificate

active

07415602

ABSTRACT:
An apparatus for processing a sequence of instructions, which comprises a LCALL instruction, a FCALL instruction and a common re-jump instruction (return), comprises a means for reading-in an instruction, to perform the read-in instruction of a means for examining the instruction. In the case of the presence of LCALL or FCALL, a stack memory is filled, while the stack is emptied in the case of the presence of a re-jump instruction. At every re-jump, a predetermined amount of re-jump information is taken from stack and supplied to a means for decoding, which is formed to access the stack again in the case where the predetermined amount of re-jump information indicates a change of the physical memory window, to finally supply the correct address for the next instruction in the instruction sequence to the means for reading in. Thereby, the same re-jump instruction can be used for a call with FCALL (outside of a current physical memory window) and a call with LCALL (within the physical memory window), without a microprocessor change, by encoding the re-jump information on the stack and by decoding them by the means for decoding. Thereby, the re-jump instruction provided for the microprocessor can be used for both jump instructions.

REFERENCES:
patent: 4432051 (1984-02-01), Bogaert et al.
patent: 5220669 (1993-06-01), Baum et al.
patent: 5261101 (1993-11-01), Fenwick
patent: 5737590 (1998-04-01), Hara
patent: 6055617 (2000-04-01), Kingsbury
patent: 0 649 084 (1995-04-01), None
“Return Address Stack Cache,” IBM Technical Disclosure Bulletin, vol. 34, No. 11, Apr. 1992, pp. 269-271.

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