Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2000-12-29
2004-05-11
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S763000, C375S372000
Reexamination Certificate
active
06735723
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an interleaving/deinterleaving processing method, a channel encoding system using it and a computer readable recording media for realizing it, and more particularly, to a method for realizing a inter-column substitution including interleaving/deinterleaving processing apparatus and method and thereof adopt reading media which can read the program, wherein the interleaving/deinterleaving operation processing apparatus and method which is used in error correction generated from a channel environment of mobile communication.
That is, the present invention embodiment the interleaving/deinterleaving, which is essential in realizing CDMA mobile communication system, and using strong application technology for effective and correct signal transfer. Especially, in mobile communication, there generated burst error by multi-channel caused multi-fading. So a codification and an interleaving can make effective transfer by changing a burst error to a random error.
DESCRIPTION OF THE PRIOR ART
In an international mobile telecommunication-2000 (IMT-2000), an interleaving/deinterleaving processing apparatus is accepted to a transmission time interval (TTI) and an utmost transfer rate is reached to 2 Mbps. At this time, transfer time interval is structured to 10~80 ms, so assuming that 384 Kbps data rate and 80 ms transfer time interval, then a memory for a first interleaving is reached to 553 Kbits, and if two RAM is used for reading and writing according to a conventional method, a memory which using the interleaving over 1 Mbits and occupied almost whole area of the chip. Moreover, thereof needed a second deinterleaving and a memory for the first and the second interleaving, so memory downsizing is necessary for making high data rate supply modem in one chip.
Another characteristics is performing an inter-column substitute before a block interleaving performing.
In here, refer to the conventional interleaving/deinterleaving structure.
First, in a three memory used structure, one is used for storing input data, another is used for the interleaving/deinterleaving sequence same as for the first memory reading address storing and the other is for storing the interleaving/deinterleaving result.
Second, improving the first structure, instead of storing the interleaving/deinterleaving sequence in the memory, producing an address through a counting machine. This structure uses two memory which divided in two structure following its use; one is uses two memory for storing input data and the interleaving/deinterleaving result, the other uses the memory for reading and writing, in turn.
Third, one memory use structure, reach to the inputted sauce data memory in two-dimension so writes in column direction, reads in column direction and changes the direction in turn.
The first and the second structure are easy in embodiment, but the memory size is fixed from 384 Kbps to 2 Mbps reached high data rate required application, so they are not good for applying in a terminal but the third structure is efficient.
However, in the IMT-2000, the interleaving process method performing inter-column substitution before a simple block interleaving, so simple column and row substitute method cannot complete the process. Because the inter-column substitution need nonlinear structure instead of the two-dimensional structure.
The conventional interleaving/deinterleaving method considers processing timing, and use two memories and during one memory writes input data, the other memory reads storing data. This method has an advantage of obtaining enough processing timing because the memory has small size when a data rate is low. However, considering an increased data and memory size, using two memories is not an advantage any more.
Furthermore, in the IMT-2000 standard, the first interleaver operates to the transfer time interval, up to 80 ms, and to receive this, the memory size has to be larger in proportion to the data rate and transfer time interval. So using two memories is resulted in make a chip to a several or using an outer memory. Therefore, memory size downsizing for the interleaving/deinterleaving to realize one modem to one chip is very important. Furthermore, different from the conventional interleaving performing method, the inter-column is preceded, so when uses one memory in writing and in reading, in column and in row respectively,
To consider the above, performing the interleaving/deinterleaving by using one memory to downsizing the memory size and making one chip modem which can support high data rate needed service is required.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an apparatus and a method for processing data burst error correction used an interleaving/deinterleaving, and an address generator to write data in basic read position by generating an address, and using one memory, records the next data thereof, and using channel encoder system to realize it.
In accordance with a first embodiment of the present invention, there is provided an interleaving performing device, including: an interleaving storing unit for sequence storing which is inputted from a writing address generating unit and from a first and a second selecting unit; the writing address generating unit for demanding a memory inter-location offset (WR_OFF) to performing a writing operation in the interleaving storing unit memory block and for generating a practically writing address, data and memory control signal; an address offset generating unit for inputting a middle value (MID_OFF) and a start signal (cal_start) for demand a memory inter-location offset (RD_OFF) from the writing address generating unit, to read in an interleaving sequence and for generating an intermediate variable (COL_OFF) which is used for the memory inter-location offset (RD_OFF) and an inter-column substitution; a reading address generating unit for increasing the address offset generating unit originated signal to as much as a symbol's memory inter-location offset (RD_OFF) and create an address for reading the interleaving storing unit to generate memory control signal; the first and the second selecting unit for selecting appropriate signal between a control signal and address in the writing address generating unit and the reading address generating unit transferred writing operation needed reading operation, and in a real interleaving operation needed reading operation; and a third selecting unit for selecting appropriate symbol in the memory output signals which are generated from the reading operation, and performed from the reading address generating unit transferred interleaving.
In accordance with a second embodiment of the present invention, there is provided a deinterleaving performing device, including: an deinterleaving storing unit for sequence storing which is inputted from a writing address generating unit and from a first and a second selecting unit; the writing address generating unit for demanding memory an inter-location offset (WR_OFF) to performing a writing operation in the deinterleaving storing unit memory block and for generating practically writing address, data and memory control signal; an address offset generating unit for inputting a middle value (MID_OFF) and a start signal (cal_start) for demand a memory inter-location offset (RD_OFF) from the writing address generating unit, to read in deinterleaving sequence and for generating an intermediate variable (COL_OFF) which is used for a memory inter-location offset (RD_OFF) and an inter-column substitution; a reading address generating unit for increasing the address offset generating unit originated signal to as much as a symbol's memory inter-location offset (RD_OFF) and create an address for reading the deinterleaving storing unit to generate memory control signal; the first and the second selecting unit for selecting appropriate signal between a control signal and address in the writing address generating unit and the reading address generating unit transferred writing
Eo Ik-Soo
Kim Kyung-Soo
Park Hyung-Il
De'cady Albert
Electronics and Telecommunications Research Institute
Gandhi Dipakkumar
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