Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-01-23
1999-06-29
Gossage, Glenn
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
395383, 395584, 711204, G06F 1200, G06F 1300, G06F 938
Patent
active
059182466
ABSTRACT:
An apparatus and method for pre-loading a cache memory based on information contained in a compiler generated program map are disclosed. The program map is generated by the compiler at the time source code is compiled into object code. For each application program, the user would have this program map stored with the object file. At the beginning of the program execution cycle, the operating system will determine whether or not a program map exists for the application. If a program map exists, the operating system will load the program map into an area of RAM designated as the program map random access memory (RAM). The program map will be used to pre-load the cache with the appropriate data and instructions for the central processing unit (CPU) to process. The program mapping would be the address location of each jump/branch target that the CPU might encounter during the execution cycle. Each of these locations represent a starting point for a new code sequence. At the start of the map will be an identifier field to mark the start of the map. The next field in the program map will provide the entry point of the starting address of the application program. If a particular application program does not have a program map, the program and cache operation will remain unchanged. This feature provides backwards compatibility with existing application programs.
REFERENCES:
patent: 5423048 (1995-06-01), Jager
patent: 5652858 (1997-07-01), Okada et al.
patent: 5687349 (1997-11-01), McGarity
patent: 5713003 (1998-01-01), DeWitt et al.
Callahan et al, "Software Prefetching," ASPLOS-N Proceedings, Apr. 1991, pp. 40-52.
Klaiber et al, "An Architecture for Software Controlled Data Prefetching," Proc. 18.sup.th Annual Inter. Symp. on Comp. Arch., May 1991, pp. 43-63.
Mowry et al, "Design & Evaluation of a Compiler Algorithm for Prefetching," Proc. 5.sup.th Inter. Conf. on Arch. Supp. for Prog. Lang. & Oper. Sys., Oct. 1992, pp. 62-73.
Mowry et al, "Tolerating Latency Through Software Controlled Prefetching in Shared-Memory Multiprocessors," Jour. of Par. and Distr. Computing 12, (1991), pp. 87-106.
Gornish et al, "Compiler Directed Data Prefetching in Multiprocessors With Memory Hierarchies," Proc. of 1990 Inter. Conf. on Supercomputing, 1990, pp. 354-368.
Chen et al, "Data Access Microstructures for Superscalar Processors with Compiler Assisted Data Prefetching," Proc. of Microcomputing 24 (1991), pp. 69-73.
Goodnow Kenneth Joseph
Ogilvie Clarence Rosser
Pricer Wilbur David
Ventrone Sebastian Theodore
Gossage Glenn
International Business Machines - Corporation
Shkurko Eugene I
LandOfFree
Apparatus and method for prefetching data based on information c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for prefetching data based on information c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for prefetching data based on information c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1387196