Apparatus and method for prediction of zero arithmetic/logic res

Details Apparatus and method for prediction of zero arithmetic/logic res Apparatus and method for prediction of zero arithmetic/logic res

1989-05-01

1990-08-07

Harkcom, Gary V.

Boots, shoes, and leggings

3647365, G06F 738

Patent

active

049473590

ABSTRACT:
The invention determines when two operands are equivalent directly from the operand without the use of an adder. In one embodiment, conditions for the sum being equal to zero are determined from half sum to carry and transmit operators derived from the input operands. These operands are used in some known types of adders and, thus may be provided from a parallel adder to the condition prediction circuitry. In another embodiment, the equations for a carry-save-adder are modified to provide a circuit specifically designed for the determination of the condition when the sum of the operands is equal to zero. This sum is equal to zero circuit greatly reduces the gate delay and gate count thus allowing the central processing unit to determine the condition prior to the actual sum of two operands. This allows the CPU to react to the condition more quickly, thus increasing overall system speed.

REFERENCES:
patent: 3983382 (1976-09-01), Weinberger
patent: 4630192 (1986-12-01), Wassel et al.

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