Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-03-23
2001-10-09
Auve, Glenn A. (Department: 2181)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S601000
Reexamination Certificate
active
06301671
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to video encoder devices, and particularly, to a methodology for reducing power consumption in MPEG-2 compliant video encoder circuits.
2. Discussion of the Prior Art
Due to the amount of computations required, MPEG-2 hardware video encoders require many logic circuits, resulting in large amounts of power consumption. For instance, studies have demonstrated that clocks provided per functional unit of a device consume 41%-73% of the total average power consumed by that functional unit, largely due to the difference between the clock switching factor and the random logic switching. This large power requirement translates to a need for extra assistance with dissipating heat, which may require additional board space and more aggressive cooling techniques such as large heat sinks and more fans. Devices consuming large amounts of power thus require more carefully designed circuits, increasing the cost of the chip and printed circuit board, and the final product in which it is housed.
For example, in a typical video encoder, on-chip memory arrays are provided. In traditional implementations of on-chip array elements, a free running oscillator
11
is usually provided as the clock input to the array
10
, as generally shown in FIG. l. Every transition of the oscillator results in the switching of a number of internal array nodes (the actual number being dependent on the design details of the array element itself) regardless of whether a read or a write was performed during the given cycle. For instance, transitions of array data and address lines between read/write cycle occur when the registers feeding the data and address lines of the on-chip array are fed with a free running (non-gated) oscillator and the data input to these registers changes for reasons other than prior to performing an array read/write. If the address register has a free running clock, each nodal transition in turn results in power dissipation.
Prior art techniques for reducing power consumption in electronic devices include the switching on/off of power supply voltages and/or clock signals to various devices when they are not used. U.S. Pat. No. 5,461,266 describes a typical technique for achieving reduced power consumption in computers by implementing a clock supply control device having the ability to stop or commence clock input to individual device components. However, the clock control device described in U.S. Pat. No. 5,461,266 implements a processor that requires many machine cycles to check the status of flags contained in an elaborate look-up table generated for tracking when a component has been brought to an unused condition before initiating stopping of the clock supply to that individual component.
It would be highly desirable to provide a computationally intensive video encoder such as an MPEG-2 video encoder with a power reduction methodology that is simple to implement, requiring minimal logic.
It would be further desirable to provide a methodology and apparatus for reducing power consumption of on-chip memory arrays in devices such as MPEG-2 compliant encoders.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a technique for reducing power consumption in MPEG-2 video encoder devices.
A further object of the present invention is to provide a technique for reducing power consumption in MPEG-2 video encoder devices by asserting clocks only when circuit logic requires them.
Still further, an object of the present invention is to provide a technique for reducing power consumption in MPEG-2 video encoder devices that disables clocks input to certain motion estimation/compensation circuitry when the motion estimation/compensation process is not being performed.
Still another object of the invention is to provide gating of a register clock input to on-chip memory arrays.
Yet another object of the invention is to provide a way to change the contents of address/data registers only when needed.
In accordance with the principles of the invention, there is provided a system for reducing power consumption in video encoder circuitry having active processing circuitry receiving first clock signals, the system comprising: a circuit implementing logic for generating a first signal indicating either an active encode processing period in a functional sub-unit of said video encoder for a current video encode operation or, indicating an idle processing period; processing detection circuitry continuously receiving second clock signals and implementing logic for generating a second signal in response to receipt of a first signal indicating idle processing periods; and, clock control circuitry responsive to the second signal for disabling input of the first clock signals to the active data processing circuitry during the idle processing periods, while concurrently enabling the second clock signals to be input to the processing detection circuitry, whereby power consumption is reduced in the active processing circuitry during the idle periods.
Advantageously, the methodology promotes the operation of logic circuits of an MPEG-2 video at a lower temperature, thus increasing product reliability. Furthermore, applications such as camcorders that require lower power will benefit from a power reduction apparatus implemented in an MPEG-2 compliant video encoder.
REFERENCES:
patent: 5452434 (1995-09-01), MacDonald
patent: 6028631 (2000-02-01), Nakaya et al.
patent: 6079022 (2000-06-01), Young
patent: 6088807 (2000-07-01), Maher et al.
patent: 6173408 (2001-01-01), Jimbo et al.
Boice Charles Edward
Kaczmarczyk John Mark
Murdock John Ashley
Vachon Michael Patrick
Woodard Robert Leslie
Auve Glenn A.
International Business Machines - Corporation
Scully Scott Murphy & Presser
LandOfFree
Apparatus and method for power reduction control in a video... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for power reduction control in a video..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for power reduction control in a video... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2607782