Apparatus and method for power management of embedded subsystems

Details Apparatus and method for power management of embedded subsystems Apparatus and method for power management of embedded subsystems

1998-10-02

2000-12-19

Etienne, Ario

Electrical computers and digital processing systems: support

Computer power control

713320, 713323, 713324, G06F 126

Patent

active

061638455

ABSTRACT:
An apparatus and method for power management of embedded electronic subsystems. A power management control circuit for managing power to an embedded subsystem includes a subsystem power node connected to a first section of the embedded electronic subsystem and a bias voltage node connected to a second section of the embedded electronic subsystem. A power switch is connected between a power supply and the subsystem power node. By separating the power subsystem node from the bias voltage node, power can be removed from the subsystem, while still providing the necessary bias voltage to the electronic static discharge (ESD) diodes. This prevents the voltages applied to the system bus by the subsystem from causing bus contention or system bus lock-ups. A power removal and restoration procedure is also disclosed.

REFERENCES:
patent: 5416351 (1995-05-01), Ito et al.
patent: 5546591 (1996-08-01), Wurzburg et al.
patent: 5724297 (1998-03-01), Noda et al.
Power Managed Second-Level Cache Control; IBM Technical Disclosure Bulletin, vol. 39, No. 04. Apr. 1996, pp. 79-82.
Automatic Disk Power Reduction For Portable Computers; IMB Technical Disclosure Bulletin, vol. 32, No. 4B, Sep. 1989, pp. 60-61.

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