Apparatus and method for plating pin grid array packaging module

Details Apparatus and method for plating pin grid array packaging module Apparatus and method for plating pin grid array packaging module

1997-02-28

1999-02-09

Bell, Janyce

Coating processes

Nonuniform coating

Mask or stencil utilized

427304, 427305, 4274301, 4274432, 118406, 118428, 118503, 118505, 118 50, 204224R, 204297M, 205122, 205125, 205136, B05D 500, B05C 300, C25D 1708

Patent

active

058691391

ABSTRACT:
An apparatus and a method for its use for plating pin grid array packaging modules, with a fixture capable of simultaneously holding a plurality of said pin grid array modules such that three-dimensional bottom surface metallurgy (BSM) is sealingly protected during plating of top surface metallurgy (TSM).

REFERENCES:
patent: 5223110 (1993-06-01), Nolan et al.
patent: 5228966 (1993-07-01), Murata
patent: 5342495 (1994-08-01), Tung
patent: 5405518 (1995-04-01), Hsieh et al.
patent: 5516416 (1996-05-01), Canaperi et al.
patent: 5522975 (1996-06-01), Andricacos et al.
Frankel, H et al.; IBM Technical Disclosure Bulletin; Plating Mask Fixture; vol. 11, No. 5; Oct. 1968, p. 464.

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