Apparatus and method for pipelined memory operations

Details Apparatus and method for pipelined memory operations Apparatus and method for pipelined memory operations

2008-04-01

2008-04-01

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S104000, C711S005000, C365S233100, C365S189040, C365S189011, C365S189030

Reexamination Certificate

active

07353357

ABSTRACT:
A semiconductor memory device has a memory core that includes at least eight banks of dynamic random access storage cells and an internal data bus coupled to the memory core. The internal data bus receives a plurality of data bits from a selected bank of the memory core. The semiconductor memory device further comprises a first interface to receive a read command from external to the semiconductor memory device and a second interface to output first and second subsets of the plurality of data bits. The first subset is output during a first phase of an external clock signal and the second subset is output during a second phase of the external clock signal. The first phase includes a first edge transition and the second phase includes a second edge transition. The second edge transition is an opposite edge transition with respect to the first edge transition.

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