Apparatus and method for performing static timing analysis...

Details Apparatus and method for performing static timing analysis... Apparatus and method for performing static timing analysis...

2007-09-11

2007-09-11

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

10777262

ABSTRACT:
An apparatus and method perform static timing analysis on an integrated circuit design. Certain pessimistic assumptions regarding slack when data launch and clock test signals are on opposite edges and derived from common logic blocks are improved by allowing the designer to identify common logic blocks, to compute the difference between maximum and minimum delays in the common logic blocks, and to improve the slack using this computed difference and a correction factor, thereby accounting for excessive pessimism in the static timing analysis that results from the common logic blocks. The apparatus and method give credit for slack in common blocks automatically, thereby allowing a large number of pessimistic slack values to be automatically corrected and reducing the workload of an integrated circuit designer in addressing the timing problems in an integrated circuit design.

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Patent Application entitled “Apparatus and Method for Performing Static Timing Analysis of an Integrated Circuit Design Using Dummy Edge Modeling,” Craig M. Darsow et al., filed Feb. 12, 2004.

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