Apparatus and method for performing single-instruction...

Details Apparatus and method for performing single-instruction... Apparatus and method for performing single-instruction...

2006-08-29

2006-08-29

Fleming, Fritz (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C712S022000, C712S026000, C712S244000

Reexamination Certificate

active

07100025

ABSTRACT:
An apparatus and method for performing single-instruction multiple-data instructions using a single multiply-accumulate unit while minimizing operational latency. The multiply-accumulate unit generates a first half and a second half of a data result. A register stores the first half of the data result. A miscellaneous-logic unit determines when to release the first half of the data result from the register to synchronize the first half and the second half of the data result.

REFERENCES:
patent: 3761922 (1973-09-01), Evans
patent: 3979701 (1976-09-01), Tomozawa
patent: 5596733 (1997-01-01), Worley et al.
patent: 6038652 (2000-03-01), Phillips et al.
patent: 6230257 (2001-05-01), Roussel et al.

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