Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1998-04-08
2001-02-06
Lintz, Paul R. (Department: 2768)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06185725
ABSTRACT:
BRIEF DESCRIPTION OF THE INVENTION
This invention relates generally to the process of implementing logic in programmable logic devices. More particularly, this invention relates to a technique of partitioning logic into a programmable logic device.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a programmable logic device
20
composed of logic array blocks
22
. Horizontally aligned logic array blocks
22
form logic array block rows
23
. Each logic array block
22
consists of a group of logic elements
24
.
Around the periphery of the programmable logic device
20
are input/output nodes
26
. Each logic element
24
and input/output node
26
can generate one or more signals that can be routed to other logic elements
24
or input/output nodes
26
through column interconnect circuitry
28
and row interconnect circuitry
30
.
FIG. 2
is a more detailed view of a logic array block
22
. The figure illustrates a set of logic elements
24
. Local interconnect circuitry
31
routes signals generated within the logic array block
22
(or signals generated externally to the logic array block which have been routed to this logic array block) to the logic elements
24
within that logic array block.
Each row of logic array blocks
23
has associated row interconnect circuitry
30
that can route signals between the different logic array blocks in a row. The columm interconnect circuitry
28
operates in a similar manner to route signals between different logic array blocks in a column.
A logic design is a description of a logic circuit that can be implemented with a programmable logic device. A logic design typically consists of a collection of logic components and input/output pins that connect together through input and output ports. Large logic designs will typically be described in a hierarchical fashion, where some of the logic components represent other logic “subdesigns”. For example,
FIG. 3
illustrates a hierarchical logic design
32
. The hierarchical logic design
32
includes element A:
1
, which includes: input/output ports
33
, logic gate
35
, and hierarchical components B:
1
, B:
2
, and D:
1
. Hierarchical component B:
1
includes component C:
1
, hierarchical component B:
2
includes component C:
2
, and hierarchical component D:
1
includes components E:
1
and E:
2
.
FIG. 4
illustrates a partially flattened hierarchical design
36
corresponding to FIG.
3
. Observe in
FIG. 4
that hierarchical component B:
1
has been flattened such that it does not include hierarchical component C:
1
. Similarly, hierarchical component B:
2
is flattened such that it does not include hierarchical component C:
2
.
Hierarchical logic designs of the type shown in
FIGS. 3 and 4
can be specified with a number of well-known entry mechanisms, such as graphical schematic entry or textual design entry (such as using the VHDL language).
When implementing a logic design in a programmable logic device, the logic design is typically synthesized into a completely flattened (non-hierarchical) network of virtual logic elements.
FIG. 5
illustrates a fully flattened hierarchical design corresponding to the design of
FIGS. 3 and 4
. The synthesized virtual logic elements are assigned to physical logic elements
24
of a programmable logic device
20
. Such an assignment is called a partitioning. Thus, partitioning refers to a process of converting a logic design to individual logical elements
24
of a programmable logic device
20
that are used to implement the logic design.
To satisfy the routing requirements of the device, a partitioning must observe the maximum number of signals that are allowed to enter or leave each logic array block
22
or each logic array block row
23
. A partitioning that minimizes the routing requirements in the device is considered superior to one that does not.
In the prior art, if a change is made to one of the hierarchical components of a design, say hierarchical component B
1
of
FIG. 3
, the entire design has to be resynthesized and re-partitioned. Alternatively, the design software can re-synthesize only those logic elements that are affected by changes to the logic design and only re-partition those logic elements that were subsequently added or altered. Unfortunately, re-partitioning only those logic elements that were altered can lead to an inferior partitioning, or in a worse case, an unsuccessful partitioning. Unsuccessful partitioning occurs when the modified logic changes the routing requirements of the unmodified logic elements, the modified logic makes demands upon routing resource pools that are shared with the unmodified logic element, or when the modified virtual logic elements cannot be assigned to their preferred logic elements because the logic elements have been previously assigned to some of the unmodified virtual logic elements.
In view of the foregoing, it would be highly desirable to provide an improved technique for partitioning a logic design into a programmable logic device.
SUMMARY OF THE INVENTION
A method of partitioning logic into a programmable logic device includes the steps of synthesizing a logic design into a network of hierarchical components. Each hierarchical component is then mapped to a minimum number of logic array blocks in a programmable logic device. The mapping operation may be performed by independently synthesizing the hierarchical components into a network of virtual logic elements, assigning the virtual logic elements to virtual logic array blocks, and mapping the virtual logic array blocks to the logic array blocks in the programmable logic device.
The technique of the invention improves partitioning, aids in the incremental re-repartitioning of logic, and improves the consistency of logic delays within similar hierarchical components.
REFERENCES:
patent: 5455775 (1995-10-01), Huber et al.
patent: 5475830 (1995-12-01), Chen et al.
patent: 5519629 (1996-05-01), Snider
patent: 5742181 (1998-04-01), Rush
patent: 5933356 (1999-08-01), Rostoker et al.
Altera Corporation
Galliani William S.
Lintz Paul R.
Pennie & Edmonds LLP
Siek Vuthe
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