Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
1997-07-15
2001-12-04
Butler, Dennis M. (Department: 2182)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S600000
Reexamination Certificate
active
06327667
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to the communication of digital signals, and more particularly to communicating timing, control, address, and data signals used in computer systems.
BACKGROUND OF THE INVENTION
In modem computer systems, relatively high speed processors manipulate data sourced from memories, and other system components that generally have slower and different operating characteristics than the processor. For example, in a system with hierarchical memories, the data can be persistently stored in relatively slow storage devices such, as disk and tape. Alternatively, the data can be sourced externally from other processors, networks, or input/output devices via I/O interfaces.
Data which are immediately manipulated by the processor are typically stored in faster, but smaller and volatile semiconductor random access memory (RAM). One or more small and high-speed cache memories are usually arranged between the processor and the RAM. The caches, relying on spatial and temporal relationship between data and addresses, store data which have a high likelihood to be used by the processor.
Cache memories can be configured to be physically separate from the processor, e.g., “off-chip.” Additional cache memories can be arranged to be co-resident with the processor on the same semiconductor die, e.g., “on-chip.” In the later case, the cache memories can be highly specialized. For example, data and instructions for manipulating the data may be stored in separate on-chip caches.
Typically, the processor, memories, and I/O components are interconnected by communication buses that transport timing, control, address, and data signals. The processor, memories, and other system components that share the data can have distinctly different electrical operating requirements and characteristics which may require multiple bus architectures.
For example, the processor and the on-chip cache memories are usually operated by control and address, or “index” signals synchronized to timing signals derived from a high-speed processor clock. The off-chip memory and system components are usually operated by signals synchronized to a slower system clock. The signals used to operate the on-chip and off-chip components, respectively, may have different frequencies, shapes, e.g. length and height, latencies, and protocols. For example, it is not unusual to run the processor clock orders of magnitude faster than the system clock. On-chip components generally run synchronously with respect to timing signals forwarded with the control and address signals, Off-chip components can run asynchronously with respect to skew controlled and radially distributed timing signals.
For these reasons, the electrical environments of the system can be partitioned into separate operating regions or “domains.” The processor, and other on-chip components process digital signals in a processor or “private” domain, and the off-chip components process the digital signals in a system or “external” domain.
Processing digital signals in a computer system having multiple operating domains presents a throughput problem. For example, should the processor require access to data that are not accessible in the private domain, e.g., data processed by on-chip high-speed digital signals, then the data needs to be accessed in the external domain using slower signaling environments.
In traditional computer systems, switching operations from one domain to another generally increase access latencies. This is a particular problem for a clock sensitive device such as the off-chip cache that is immediately adjacent and external to the processor chip. In traditional computer systems, the first level of off-chip cache is usually restricted to operate only in the external domain, thus drastically decreasing throughput.
Therefore, there is a need for an apparatus and method which can improve the throughput of computer systems having multiple operating domains and clock sensitive components.
SUMMARY OF THE INVENTION
An apparatus and method in a digital signal processing system, such as a computer system, operates a clock sensitive device, e.g., a synchronous memory, in a plurality of operating domains. The first domain has first timing and control signals synchronized to a first clock. In response to an event, for example, a cache data miss, the apparatus dynamically transitions the operation of the synchronous memory to a second domain having second timing and control signals synchronized to a second clock.
The first timing and control signals are substantially different in frequency, shape, and protocol than the second timing and control signals. The first clock for synchronizing the first timing and control signals can a processor clock to synchronize the communication of address and data signals with a processor of the computer system, and the second clock can be a system clock to synchronize communication of the address and data signals with an asynchronous data processing device such as random access memory operating in the second domain.
The apparatus can include an issue state machine, responsive to the event, for generating an issue signal. An address generator, in response to the issue signal, generating an address signal of the data to be communicated, and a clock generator, also in response to the issue signal, generating an access clock signal. The clock signal is used to propagate the address signal in either the first or second domain.
While processing the cache data miss at a first address in the second domain, the synchronous memory can continue to operate in the first domain. In response to completing the processing of the miss at the first address, the synchronous memory receives the missing data in the second domain. While processing the miss at the first address, the apparatus can increment the first address to a second address, and the processing of missing data at the second address can be initiated before the processing of the miss, e.g. receiving the data, at the first address completes.
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Bannon Peter J.
Hetherington Ricky C.
Butler Dennis M.
Compaq Computer Corporation
Conley & Rose & Tayon P.C.
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