Apparatus and method for minimizing the delay times in a semicon

Details Apparatus and method for minimizing the delay times in a semicon Apparatus and method for minimizing the delay times in a semicon

1997-09-17

2000-11-14

Lintz, Paul R.

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

G06F 1750

Patent

active

061484342

ABSTRACT:
A method and apparatus for lowering the power dissipation for a semiconductor IC without adverse effects on its operation. The method takes into consideration the timing and function of the IC. The methods includes an analysis step to determine the delay time of each logic path by using test patterns, a classifying step for the logic paths corresponding to the delay times on the logic paths, a marking step for a class mark of the group classified in the classifying step to nodes of each logic path, a shrinking step for reducing the size of an element or a basic cell connected to the nodes having the mark of the smaller delay time group in the classified groups, and a confirming step for the delay times on the logic paths.

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