Apparatus and method for minimizing DRAM recharge time

Details Apparatus and method for minimizing DRAM recharge time Apparatus and method for minimizing DRAM recharge time

1996-05-21

1997-09-02

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Data refresh

365203, G11C 700

Patent

active

056639163

ABSTRACT:
A Dynamic random access memory has multiple registers dedicated to each column, and is controlled to refresh by reading multiple bit values from distinct capacitance storage cells consecutively, followed by consecutive refresh steps for the same capacitance storage cells equal in number to the number of consecutive read steps. As each bit value is read. it is stored in a distinct bit register reserved for that cell. The interleaved refresh provided minimizes DRAM access time, and provides a memory architecture wherein distinct, separate register arrays may be dedicated to and support distinctly different functions, such as servicing a CPU and a video system.

REFERENCES:
patent: 5359566 (1994-10-01), Furuyama
patent: 5410505 (1995-04-01), Furuyama
patent: 5467303 (1995-11-01), Hasegawa et al.
patent: 5530670 (1996-06-01), Matsumoto

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