Apparatus and method for minimizing address hold time in asynchr

Details Apparatus and method for minimizing address hold time in asynchr Apparatus and method for minimizing address hold time in asynchr

1997-10-31

1999-08-24

Dinh, Son T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365194, 3652335, G11C 800

Patent

active

059432888

ABSTRACT:
A write control circuit and method for an asynchronous SRAM that minimizes the write address hold time required to prevent data from being written to incorrect addresses in the memory. The write control circuit temporarily disables a write circuit in the memory whenever the memory address changes. The delay of the write control circuit from input to output is shorter than the delay of a decoder in the memory.

REFERENCES:
patent: 4947374 (1990-08-01), Wada et al.
patent: 5214609 (1993-05-01), Kato
patent: 5245573 (1993-09-01), Nakaoka
patent: 5428580 (1995-06-01), Kawashima et al.
patent: 5640363 (1997-06-01), Futurani et al.

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