Electrical computers and digital processing systems: memory – Address formation – In response to microinstruction
Patent
1997-03-03
2000-10-31
Peikari, B. James
Electrical computers and digital processing systems: memory
Address formation
In response to microinstruction
711214, 711202, 711219, 711125, 711144, 711145, G06F 1210, G06F 1206
Patent
active
061417408
ABSTRACT:
A superscalar microprocessor implements a microcode instruction unit that patches existing microcode instructions with substitute microcode instructions. A flag bit is associated with each line of microcode in the microcode instruction unit. If the flag bit is asserted, the microcode instruction unit branches to a patch microcode routine that causes a substitute microcode instruction stored in external RAM to be loaded into patch data registers. The transfer of the substitute microcode instruction to the patch data registers is accomplished using data transfer procedures. The microcode instruction unit then dispatches the substitute instructions stored in the patch data registers and the substitute instruction is executed by a functional unit in place of the existing microcode instruction.
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Mahalingaiah Rupaka
Miller Paul K.
Advanced Micro Devices , Inc.
Merkel Lawrence J.
Peikari B. James
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