Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-04-07
2004-01-13
Bragdon, Reginald G. (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S104000
Reexamination Certificate
active
06678804
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory access control apparatus and method for reducing the frequency with which memory is accessed during printing.
2. Background of Related Art
An A-4 size black and white image data at 600 dpi occupies 4 MB of memory. A color image data having the same resolution and size as the black and white image data occupies 128 MB of memory, 32 times that of a black and white image. In a printer, data is read from and written to memory several times each time a sheet is printed.
For example, in order to perform read/write operations, a processor dedicated to image processing has been used, and an acceleration method, such as the use of separate CPU and image data busses, has been adopted.
These conventional acceleration methods increase manufacturing cost of printers.
In addition, for example, a printer printing 40 sheets of paper per minute, transfers and renderings 512 MB or more of data per 1.5 seconds (actually, transfer of several sets of 128-MB data). The conventional methods cannot cope with the transfer and rendering of such large volume of data.
In addition, cache memory may be used to accelerate processing of data by reducing the frequency with which memory is accessed. For example, Published Unexamined Patent Application No. 5-225059 and Published Unexamined Patent Application No. 4-100164 disclose management systems of cache memory.
However, since the structure of cache memory cannot usually be changed, the frequency with which memory is accessed may not be reduced if the structure of the cache memory is not suitable to the contents of processing of a program.
Further, if cache memory is used, it is not possible to completely omit accesses to areas where data has not been written.
Therefore, the need exists for a memory access control apparatus and method which reduces the frequency with which memory is accessed during read and write operations.
SUMMARY OF THE INVENTION
The present invention is performed in consideration of the problems of conventional technology described above. An object is to provide a memory access control apparatus and method for reducing the frequency with which memory is accessed in processing data, such as image printing and the like.
In addition, another object of the present invention is to provide a memory access control apparatus and method for reducing the frequency with which memory is accessed in image printing and the like, where conventional methods such as a method of using cache memory cannot achieve the objects.
Still another object of the present invention is to provide a memory access control apparatus and method for reducing the frequency with which memory is accessed, by omitting accesses to memory areas where data has not been written or modified.
In order to achieve the above objects, a first memory access control apparatus comprises: write management means for accepting the assignment of a plurality of blocks set in a storing area of memory where data can be read and written and managing whether data writing has already occurred or not to each of these blocks; and read access control means for accepting the setup of initializing data written in the plurality of blocks at first and sending back data written in any one of the plurality of blocks or the initializing data set in this block to an access source according to whether data writing has already occurred or not to this block when a read access occurs to this block.
Preferably, in the read access control means, the initializing data is commonly set to the plurality of blocks.
Still preferably, when a read access occurs to any one of the plurality of blocks, the read access control means sends back data to an access source after reading the data from this block if the data has already been written in this block, and if not, the read access control means sends back the initializing data, set to this block, to the access source.
A second memory access control apparatus comprises: a write management means for accepting the assignment of a plurality of blocks set in a storing area of memory where data can be read and written and managing whether data has already been written in each of these blocks; and write access control means for accepting the setup of initializing data written in the plurality of blocks for the first time and writing the initializing data, which is set, and data to be written with a write access in any one of the plurality of blocks, or the data, which is to be written, in this block according to whether data has already been written in this block when the write access occurs to this block.
Further preferably, in the write access control means, the initializing data is commonly set to the plurality of blocks.
Still further preferably, the write access control means writes data in any one of the plurality of blocks if the data has already been written in this block when a write access occurs to this block, and if not, the write access control means writes the initializing data in this block, and writes data making this block in such a state that the data to be written is written.
A memory access control apparatus according to the present invention is suitable to acceleration of image processing, a large part of the background data is filled with the same contents, is processed, as cases of generating computer graphic scenes and printing an office document with a printer.
The memory access control apparatus according to the present invention uses a memory area storing image data with dividing the area in a plurality of blocks corresponding to respective background graphics according to the setup by a image processing program, and accepts from the image processing program the setup of background image data to be stored in respective blocks (initializing data).
The memory access control apparatus according to the present invention writes background image data (initializing data) in a block for the first time if a image processing program performs the first write access to this block, and further writes the data that the image processing program is going to write.
Hereafter, the memory access control apparatus according to the present invention does not write the initializing data if a further write access occurs to a block where the write access has already been performed, but writes only the data that the image processing program is going to write.
In addition, the memory access control apparatus according to the present invention sends back the initializing data to the image processing program instead of sending back to the image processing program the data that is read from a block if the write access has not occurred to this block and only the read access occurs.
In this manner, by sending back the initializing data without actually writing image data in the memory, which is a part becoming a background, until the write access occurs, the memory access control apparatus according to the present invention omits a memory access by omitting write processing of the initializing data (background data) in a block to which a write access is not performed.
The write management means has, for example, a management table storing data with corresponding to respective blocks obtained by dividing a storing area of memory, and manages whether a write access has not occurred at all to each of these blocks or one or more write accesses have occurred.
The read access control means accepts the setup of, for example, background image data as the initializing data, and refers to the management table when a read access occurs to a block. Further, the read access control means sends back the initializing data, which is set, to a program and the like performing the read access if the data in the table that corresponds to a block to which the read access is performed shows that the write access has not occurred at all to this block.
In addition, if the data in the table that corresponds to a block to which the read access is performed shows that one or more write accesses have occurred to this
Funatogawa Kazuo
Kato Yoshiharu
Ogata Masanobu
Bragdon Reginald G.
F. Chau & Associates LLP
International Business Machines - Corporation
Trepp Robert M.
Vital Pierre M.
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