Apparatus and method for matching a clock delay to a delay throu

Details Apparatus and method for matching a clock delay to a delay throu Apparatus and method for matching a clock delay to a delay throu

1995-12-22

1997-07-29

Dinh, Son T.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 365210, G11C 800

Patent

active

056527322

ABSTRACT:
A memory device including a memory array and a series of sense amplifiers coupled to the memory array. The memory array includes numerous memory cells. A clock transmission line receives a clock signal and forms a clock word line within the memory device. A circuit is coupled to the clock transmission line and includes at least one transistor device coupled to the clock transmission line to receive the clock signal. The circuit also includes a clock output coupled to one of the sense amplifiers.

REFERENCES:
patent: 5327394 (1994-07-01), Green et al.
patent: 5343438 (1994-08-01), Choi et al.
patent: 5438548 (1995-08-01), Houston
patent: 5455802 (1995-10-01), McClure

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