Apparatus and method for masking input of invalid data...

Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis

Reexamination Certificate

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C713S502000, C713S503000, C713S401000, C365S189150, C365S193000, C365S195000, C365S196000

Reexamination Certificate

active

07908507

ABSTRACT:
To provide a data fetch circuit, which reliably cuts off transmission of a high impedance state of a data strobe signal even if a manufacture condition or an operation condition is changed, and a control method thereof. The data fetch circuit includes an RL measuring part10measuring a latency measurement value RLB from an input of a read instruction signal RD to a valid edge of a data strobe signal DQS and an RL count comparing part30outputting a BL count start signal BST giving an instruction of a cancel of the cut-off of the data strobe signal DQS after standing by during the time based on the latency measurement value RLB in accordance with an input of a delay read instruction signal RDD.

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patent: 6621760 (2003-09-01), Ahmad et al.
patent: 6680866 (2004-01-01), Kajimoto
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patent: 6853594 (2005-02-01), Wu et al.
patent: 7038953 (2006-05-01), Aoki
patent: 7177230 (2007-02-01), Huang
patent: 7619404 (2009-11-01), LaBerge
patent: 2005/0152209 (2005-07-01), Shin et al.
patent: 2003-085974 (2003-03-01), None

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