Apparatus and method for mapping a redundant memory column to a

Details Apparatus and method for mapping a redundant memory column to a Apparatus and method for mapping a redundant memory column to a

1995-05-10

1996-11-05

Nelms, David C.

Static information storage and retrieval

Read/write circuit

Bad bit

3652257, 36523003, G11C 700

Patent

active

055724701

ABSTRACT:
An apparatus maps one of a plurality of redundant memory columns, each having a redundant memory cell, to an address of a defective memory column in a memory device that communicates with an external data bus having one or more data-bit lines and an address bus. An address decoder receives an address signal on the address bus and generates an enable signal to enable the redundant cell of the redundant column when the value of the address signal equals the address of the defective memory column. A bit-select bus has one or more bit-select lines each associated with one of the data-bit lines. Each bit-select line can carry a bit-select signal. Each of a plurality of bit-line selectors is associated with one of the redundant columns and communicates with the bit-select bus. In response to an associated enable signal, each bit-line selector can generate the bit-select signal on the bit-select line associated with a desired data-bit line. An interface circuit couples the redundant cell to the desired data-bit line in response to the bit-select signal.

REFERENCES:
patent: 4471472 (1983-09-01), Young
patent: 4601019 (1986-07-01), Shah et al.
patent: 5195057 (1993-03-01), Kasa et al.
patent: 5299164 (1994-03-01), Takeuchi et al.
patent: 5307316 (1994-04-01), Takemae
patent: 5381370 (1995-01-01), Lacey et al.

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