Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output data buffering
Reexamination Certificate
2001-07-26
2004-04-20
Gaffin, Jeffrey (Department: 2182)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output data buffering
C710S057000, C710S112000
Reexamination Certificate
active
06725296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention is directed to an improved data processing system. More specifically, the present invention is directed to an apparatus and method for managing work and completion queues using head and tail pointers.
2. Description of Related Art
In a System Area Network (SAN), the hardware provides a message passing mechanism that can be used for Input/Output devices (I/O) and interprocess communications (IPC) between general computing nodes. Processes executing on devices access SAN message passing hardware by posting send/receive messages to send/receive work queues on a SAN channel adapter (CA). These processes also are referred to as “consumers.”
The send/receive work queues (WQ) are assigned to a consumer as a queue pair (QP). The messages can be sent over five different transport types: Reliable Connected (RC), Reliable Datagram (RD), Unreliable Connected (UC), Unreliable Datagram (UD), and Raw Datagram (RawD). Consumers retrieve the results of these messages from a completion queue (CQ) through SAN send and receive work completion (WC) queues. The source channel adapter takes care of segmenting outbound messages and sending them to the destination. The destination channel adapter takes care of reassembling inbound messages and placing them in the memory space designated by the destination's consumer.
Two channel adapter types are present in nodes of the SAN fabric, a host channel adapter (HCA) and a target channel adapter (TCA). The host channel adapter is used by general purpose computing nodes to access the SAN fabric. Consumers use SAN verbs to access host channel adapter functions. The software that interprets verbs and directly accesses the channel adapter is known as the channel interface (CI).
Target channel adapters (TCA) are used by nodes that are the subject of messages sent from host channel adapters. The target channel adapters serve a similar function as that of the host channel adapters in providing the target node an access point to the SAN fabric.
The SAN channel adapter architecture explicitly provides for sending and receiving messages directly from application programs running under an operating system. No intervention by the operating system is required for an application program to post messages on send queues, post message receive buffers on receive queues, and detect completion of send or receive operations by polling of completion queues or detecting the event of an entry stored on a completion queue, e.g., via an interrupt.
Traditional Peripheral Component Interconnect (PCI) based adapters use queues that are managed by a microprocessor. Such management by a microprocessor involves a queue management software application being run by the microprocessor to manage the queue(s). The execution of software instructions always results in performance losses when compared to purely hardware based operations. Therefore, it would be beneficial to have an apparatus and method for managing queues entirely in hardware and thereby improve performance of the system. Moreover, it would be beneficial to have such an apparatus and method for managing queues in a channel adapter of a system area network.
SUMMARY OF THE INVENTION
The present invention provides an apparatus and method for managing work and completion queues using head and tail pointers. With the apparatus and method of the present invention, queue head and tail pointers are maintained in the channel interface and the host channel adapter. The head and tail pointers in the host channel adapter include a queue page table index and a queue page index for identifying a position within the queue.
For work queues, the tail pointer in the channel interface is used to identify a next position where a work queue entry may be written. The head pointer in the channel interface is used only to determine whether the work queue is full or not. The head pointer in the host channel adapter is used to identify a next work queue entry for processing by the host channel adapter. The tail pointer in the host channel adapter is used by the host channel adapter to determine if the queue is empty.
For completion queues, the head pointer in the channel interface is used to identify a next completion queue entry to be processed. The tail pointer in the channel interface is used only to determine whether the completion queue is empty or not. The tail pointer in the host channel adapter is used to identify a next position in the completion queue to which the host channel adapter may post a completion queue entry. The head pointer in the host channel adapter is used by the host channel adapter to determine if the queue is full.
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Craddock David F.
Gregg Thomas Anthony
Judd Ian David
Pfister Gregory Francis
Recio Renato John
Gaffin Jeffrey
Kim Harold
Salys Casimer K.
Walder, Jr. Stephen J.
Yee Duke W.
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