Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-07-31
2007-07-31
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S037000, C714S039000
Reexamination Certificate
active
10779140
ABSTRACT:
In some embodiments, a method and apparatus for maintaining data integrity following parity error detection are described. In one embodiment, the method includes the blockage of bus transactions in response to detection of a parity error. Once bus transactions are suspended, a parity error handler routine is invoked to perform parity error recovery according to stored transaction information regarding an error bus transaction of the detected parity error. In one embodiment, the stored information includes a bus master that caused the error, as well as an address associated with the corrupt data for which the parity error was asserted. In one embodiment, data logging is performed to track the bus masters associated with error bus transactions to enable identification of problematic or old hardware devices. Other embodiments are described and claims.
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PCT International Search Report for co-pending PCT Application No. PCT/US2005/002044, mailed Jun. 1, 2005.
Edirisooriya Geetani R.
Joshi Aniruddha P.
Lee John P.
Baderman Scott
Blakely , Sokoloff, Taylor & Zafman LLP
Bonura Tim
Intel Corporation
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