Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2000-04-12
2002-03-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S101000, C326S047000
Reexamination Certificate
active
06356116
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to clock distribution in integrated circuits. In particular, this invention relates to providing a low skew clock signal using clock buffer circuits in sub-blocks of an integrated circuit.
2. The Background Art
In very large scale integrated circuits, every sub-block which constitutes the whole chip is synchronized to either the rising edge or the falling edge of a reference clock source. However, due to physical separation and differential loading of sub-blocks, transition edges may vary slightly between sub-blocks. This variation is called skew.
There are many techniques used to minimize skew. One clock distribution scheme, known as H-tree clock distribution, attempts to minimize skew by equalizing the distance between the origin of the clock signal and the various destination sub-blocks of the clock signal.
FIG. 1
is a schematic diagram showing an H-tree clock distribution scheme in accordance with the prior art. In the H-tree clock distribution scheme
10
, a reference clock signal is applied at point
12
. From point
12
, the clock signal propagates to points
14
and
16
. From point
14
the signal propagates to points
18
and
20
, and from point
16
the signal propagates to points
22
and
24
. Ideally, the clock signal reaches points
18
,
20
,
22
and
24
at the same time. If this is the case, then there is no skew.
The H-tree employs multiple layers, depending on the complexity of the chip. If another layer is desired, points
26
,
28
,
30
,
32
,
34
,
36
,
38
,
40
,
42
,
44
,
46
,
48
,
50
,
52
,
54
and
56
should receive the clock signal simultaneously. In the next layer, points
58
,
60
,
62
,
64
and all other similarly situated points (not shown) should also receive the clock signal simultaneously.
At the end points of the clock tree, the circuits receiving the clock signals may differ in their impedance, or loading. These loading differences result in differing propagation delays along the branches of the tree, and result in skew. To balance loading, dummy loads may be implanted at receiving points or, alternatively, end point driving circuit sizes may be trimmed.
Balancing loading using existing methods has disadvantages. If imbalances are large, dummy loads may require excessive silicon real estate. Also, changing the circuit size at one end point by adding dummy loads or trimming the circuit size results in changing the relative loading at other equivalent end points. Thus, all equivalent end points may then require adjustment. When there are many end points, adjusting the loading at all end points is non-trivial.
SUMMARY OF THE INVENTION
A clock buffer circuit is disclosed. The clock buffer circuit is included in each sub-block of a clock distribution structure in an integrated circuit. Each clock buffer circuit comprises a plurality of driving inverters, and each clock buffer circuit presents an equal input load to the previous driver, regardless of the amount of load in the sub-block circuit. In each sub-block, the clock buffer circuit is connected to provide an output including the combined signals of a portion of the inverters. The portion is approximated by the load of the circuit in the sub-block divided by the load of the circuit in the sub-block having the greatest load of any sub-block. The outputs of inverters not connected to the load of the sub-block circuit are wired to power and ground terminals. Each driving inverter may comprise a pMOS FET paired with an nMOS FET. A method for designing such a clock buffer circuit is also disclosed.
REFERENCES:
patent: 4949565 (1990-08-01), Knecht et al.
patent: 5111075 (1992-05-01), Ferry et al.
patent: 5760610 (1998-06-01), Naffziger
patent: 5828870 (1998-10-01), Gunadisatra
patent: 5831459 (1998-11-01), McDonald
patent: 5838186 (1998-11-01), Inoue et al.
patent: 5911063 (1999-06-01), Allen et al.
patent: 5923188 (1999-07-01), Kametani et al.
patent: 6025740 (2000-02-01), Fukuyama
Restle, et al., “Measurement and Modeling of On-Chip Transmission Line Effects in a 400 MHz Microprocessor”, IEEE Journal of Solid-State Circuits, vol. 33, No. 4, Apr. 1998, pp. 662-665.
Ritchie David B.
Sun Microsystems Inc.
Thelen Reid & Priest LLP
Tokar Michael
Tran Anh Q.
LandOfFree
Apparatus and method for low skew clock buffer circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Apparatus and method for low skew clock buffer circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Apparatus and method for low skew clock buffer circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2864400