Apparatus and method for limiting data transmission rates

Details Apparatus and method for limiting data transmission rates Apparatus and method for limiting data transmission rates

2007-01-23

2007-01-23

Du, Thuan (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S501000, C713S503000

Reexamination Certificate

active

10767964

ABSTRACT:
A rate limiting circuit for data stream transmissions provides a generated clock signal to a buffer interposed between source and destination components so as to programmably adjust the maximum rate that data can be passed through the buffer. A counter is incremented by one each (1+RLmax) cycles of a clock signal, where RLmaxis the larger of a user programmable value (RL) and a manufacturer one-time programmed value (SERL). A controller receiving a request to access the buffer for a read or write operation, checks the count of the counter before activating the access enable line. If the count is greater than zero, then the controller activates the access enable line while decrementing the counter by one. If the count is zero, however, then the controller waits until the count is greater than zero before activating the access enable line to grant the request.

REFERENCES:
patent: 4596026 (1986-06-01), Cease et al.
patent: 5701514 (1997-12-01), Keener et al.
patent: 6658582 (2003-12-01), Han

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