Electronic digital logic circuitry – Interface – Logic level shifting
Reexamination Certificate
2001-05-04
2003-07-29
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Interface
Logic level shifting
C326S081000, C327S333000
Reexamination Certificate
active
06600338
ABSTRACT:
FIELD OF THE INVENTION
This present invention relates to digital interface circuitry. More specifically, it relates to voltage level shifters.
BACKGROUND OF THE INVENTION
As digital circuitry and systems have evolved, they have been designed to utilize steadily lower supply voltage levels. For example, early Transistor-Transistor-Logic (TTL) digital logic circuits typically operated from a 5 volt (V) power supply. As the need for power efficiency has grown, primarily with respect to mobile devices, the typical power supply voltage for devices dropped to 3V and, now, devices designed to operate from 1.8V supply levels dominate the market. Also, as the transistor geometries for integrated circuit technology have dropped, some devices are unable to operate using higher voltage supply levels. Further, lower voltage levels reduce output voltage swings and, consequently, the noise produced by the circuit.
However, many architectural standards, such as bus standards, were developed when a different logical voltage level was the norm. Also, systems may incorporate devices having different supply voltage requirements. For example, a system may include a processor, memory controller and memory that are designed to operate using 1.8V, while the system bus may be designed to operate using 3.3V of have come to operate traditionally. For example, the Peripheral Control Interface (PCI) Local Bus is designed to operate using 5V and 3.3V signaling levels. See the PCI Local Bus Specification version 2.2, herein incorporated in its entirety for all purposes.
FIG. 1
illustrates an example of a system architecture
10
utilizing a PCI local bus
40
. A microprocessor
20
directly interfaces to a cache
22
and memory controller
30
via the processor bus. Memory controller
30
also interfaces to a dynamic random access memory (DRAM) device
32
and to PCI local bus
40
. The memory controller
30
provides a bridge to the PCI bus from the processor bus and handles access to DRAM
32
and the other devices coupled to PCI local bus
40
for the processor
20
. Architecture
10
includes a representative selection of peripheral devices, e.g. network interface
42
for communications with an external network such as a local area network (LAN), graphics interface
44
for driving a video output, peripheral interface
46
for interfacing to other peripheral devices, such as keyboards, modems, etc., and disk controller
50
for controlling bulk storage to disk
52
.
Today, processor
20
, cache
22
, memory controller
30
and DRAM
32
are often designed for use with a 1.8V supply. However, as noted above, the PCI standard currently calls for logic signaling levels based on 3.3V or 5V. This raises the problem of interfacing between devices operating using different supply levels. For example, interfacing the output from a higher voltage device, such as a 5V device, to the input of a lower voltage device, such as a 3.3V device, can forward bias the Electrostatic Discharge (ESD) protection diode typically coupled to the input pad.
Systems may incorporate devices operating from a variety of supply sources having different levels.
FIG. 2
is a diagram of a clock generation architecture
60
wherein a system clock source
80
operating from voltage supply V
DD
IR, e.g. 3V, produces a reference clock signal RefCLK that is input to a Direct Rambus Clock Generator (DRCG) circuit operating from another voltage supply V
DD
, e.g. 1.8V, and producing a Bus Clock signal based on another supply voltage V
DD
IPD. The Bus Clock, in turn, drives Rambus DRAMs (RDRAM)
92
and
94
, which are controlled by memory controller
90
. The Rambus DRCG
70
, controller
90
, and RDRAMs
92
and
94
operate using the Rambus Signal Level (RSL), wherein a logic ‘1’ is represented by 1.0V and a logic ‘0’ is represented by 1.8V, which is the Rambus supply voltage. See Direct Rambus Clock Generator, Document DL-0056, Version 1.2, Rambus Inc., November 2000, herein incorporated in its entirety for all purposes.
In order to allow an output operating from one voltage level to drive an input operating from a lower voltage level, an input level translator is typically required.
FIG. 3
illustrates one example of an input level translator relating to the clock generation architecture
60
of FIG.
2
. An output pin of clock source
80
includes an output driver
82
that operates from the supply voltage V
DD
IR, which typically ranges from 1.3V to 3.3V. The output signal from output driver
82
reflects the voltage level of V
DD
IR. The output driver
82
drives an input pin of DRCG
70
, which includes an input comparator
72
that operates from supply voltage V
DD
IPD. DRCG
70
also has an input that receives V
DD
IR, which is divided by resistors
74
and
76
to obtain a threshold voltage that is input to comparator
72
. Comparator
72
compares the voltage signal received from output driver
82
with the threshold voltage obtained by dividing V
DD
IR in order to generate a received signal having logic voltage levels that reflect the voltage level V
DD
IPD.
Conventional input level shifters appear in a variety of forms, such as operational amplifier network, resistive divider network, or source follower.
FIG. 3
illustrates an example of a combination resistive divider and operation amplifier, where comparator
72
is implemented as an operational amplifier.
FIG. 4
illustrates an example of a source follower input circuit
100
composed of transistor
102
, input resistor
104
and source resistor
106
. In source follower circuit
100
, a higher voltage signal received at DIN is reflected at the source of transistor
102
, which is coupled to DOUT. The voltage levels appearing at DOUT are determined by the magnitude of supply voltage V
DD
I coupled to the drain of transistor
102
. A variety of conventional level shifter circuits are shown in U.S. Pat. Nos. 6,160,421; 6,097,215; 5,986,472; 5,973,508; 5,867,010; 5,757,712, 5,751,168; 5,663,663; 5,534,798; and 5,534,795, herein incorporated by reference for all purposes.
Conventional level shifters have a limited ability to shift from an external voltage level to an internal voltage level. Source follower circuits are dependent on the threshold voltage Vt of the transistor and tolerate only a narrow range between the external voltage level and the internal supply voltage. (?) Consequently, the source follower circuits must be tuned to each particular application. In addition, source followers do not provide gain for the input signal. In resistive divider circuits, the ratio of the resistors must be selected for the relationship between the external and internal voltage sources for the particular application and, as a result, cannot tolerate much variation in the external supply voltage. Also, the introduction of resistance to the receive path will slow the response of the input circuit making resistive dividers unsuitable for high speed applications.
Operational amplifier based circuits can be configured to introduce gain to the input signal path. However, the gain of the operation amplifier is determined by the ratio of the feedback resistance to the input resistance for the amplifier. This ratio is fixed and must be designed for a specific ratio of external to internal voltage levels. The resistance also tends to slow the circuit, resulting in poor high speed performance. For a differential input amplifier circuit, transistors must generally be stacked and a low internal voltage supply level, e.g. VDD less than 2Vt, the differential pair of the amplifier will run out of headroom to operate. In other words, the supply voltage level becomes insufficient to accommodate the output swing of the circuit without introducing distortion. For a single-ended input amplifier circuit, the gain offset can become quite large because the current source for the circuit may be pushed into its linear operating region. This causes distortion of the output signal for the receiver, such as duty cycle error. This occurs because there is a higher gain level when the data signal is higher, b
Kizer Jade
Lau Benedict
Nguyen Huy
Vu Roxanne
Chang Daniel
Rambus Inc.
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